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研究生:何祈慶
研究生(外文):HO, CHI-CHING
論文名稱:異質整合積體電路封裝技術開發
論文名稱(外文):Heterogeneous Integration IC Package Assembling Technology Development
指導教授:鍾翼能鍾翼能引用關係
口試委員:許釗興張隆益鍾翼能
口試日期:2023-06-21
學位類別:碩士
校院名稱:國立彰化師範大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2023
畢業學年度:111
語文別:中文
論文頁數:52
中文關鍵詞:高效能運算高頻寬記憶體矽中介層扇出型內埋橋接晶圓環氧樹脂熱膨脹係數
外文關鍵詞:High Performance ComputingFan-out Embedded Bridge DieEpoxy Molding CompoundCoefficient of Thermal ExpansionRedistribution Layer
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近年來半導體產品成長快速,高效能運算(HPC)產品及眾多功能於整合一個封裝體中已成為市場產品主流趨勢。為滿足高效能運算需求,晶圓需容納更多的電晶體來滿足,且摩爾定律每兩年增加一倍的積體電路上可容納的電晶體數目已達到尺寸微縮的物理極限,因此小晶片(Chiplet)及搭配異質整合的封裝技術被視為延續摩爾定律的解決方案及滿足高效能運算需求。
異質整合的封裝方案中,目前最成熟的產品為2.5D IC,具有滿足線寬線距小於2um的高密度設計需求,也可結合高頻寬記憶體(HBM)滿足電性需求優勢。但2.5D IC的複雜封裝流程及高單價的矽中介層(Silicon Interposer)造成市場不斷尋求低成本的解決方案,因此提出採用橋接晶圓 (bridge die)搭配扇出型(Fan-out)封裝的重新佈線(RDL, Redistribution Layer)技術來作為2.5D IC的替代方案,稱此封裝產品為扇出型內埋橋接晶圓封裝(FO-EB)。
在本文中將以模擬的角度選擇適合的材料來搭配FO-EB電子封裝,藉由環氧樹脂 (Epoxy Molding Compound)的選擇來解決複合材料中不同熱膨脹係數(CTE)介面造成的翹曲問題,完成封裝後再做樣本的翹曲量測及可靠度的測試,確保此結構具有量產性。
Semiconductor products have grown rapidly recently. Integrating more function die in one package is the mainstream for IC marketing trend, especially for high performance computing (HPC) and networking products. High performance package requirement includes larger die size with density transistor, and advance wafer node to provide high performance. As Moore’s law nears its physical limits and has high cost for the advanced silicon node, the idea for cost saving and chiplet concept can meet time to market, split die and heterogeneous integration in package.
In the current integration package, 2.5D IC is the mature package to fulfill electronic performance. It has fine line width/space small than 2/2 um to get die to die high density IO interconnection. But the high cost structure with Through Silicon Interposer (TSI) and complex assembly process flow are the weakness for the platform. Therefore, we have developed the Fan-out Embedded Bridge Die (FO-EB) as alternative solution for low cost and heterogeneous integration.
In this thesis, it will do the warpage simulation to select the suitable material for FO-EB assembly process, and focus on epoxy molding compound. The CTE mismatch is key concern for warpage performance, it may cause fine line width/space redistribution layer (RDL) broken. Finally, we will measure the package warpage performance by shadow moiré and verify by reliability test with FO-EB.
目錄
中文摘要………………………………................................………………………i
英文摘要………………………………………………………………………...ii
誌謝……………………………………………………………………………….iii
目錄………………………………………………………………………………iv
表目錄…………………………………………………………………………......vi
圖目錄……………………………………………………………………............vii
第一章緒論……………………………………………………………………... 1
1.1研究背景與現況……………………………………………………….1
1.2研究動機……….……………………………………………………... 2
1.3研究目的……………………………………………………………….7
1.4論文架構……………………………………………………………….8
第二章電子封裝產品介紹及演進…….................................………………….10
2.1 電子封裝產品目的…………..............................................................10
2.2 打線接合封裝產品製程介紹…………............................………......10
2.3 覆晶技術封裝產品製程介紹………..........…………………………13
2.4 系統級封裝產品製程介紹……..........………………………………15
2.5 先進封裝產品製程介紹……...……………………………………16
第三章實驗步驟與方法………………………………………………………18
3.1 測試樣本封裝資訊介紹……………………………………………18
3.2 異質整合封裝流程介紹……………………………………………21
3.3 封裝材料選擇(環氧樹脂一)介紹……...............……………………22
3.4 封裝材料選擇(環氧樹脂二)介紹……...........………………………24
3.5 封裝材料選擇(玻璃載體)介紹……………………………………26
3.6 翹曲量測方法介紹......................……………………………………27
第四章實驗結果與討論………………………………………………………. 31
4.1異質整合電子封裝…...........................................................…………31
4.2封裝樣品翹曲行為量測結果...................................…………………31
4.3封裝樣品翹曲量測比較...........................................…………………41
4.4封裝樣品可靠度測試結果.......................................................………43
第五章結論與未來展望………………………………………………………45
5.1結論……………………………………………………………45
5.2 未來展望……………………………………………………………45
參考文獻……………………………………………………….…………………47


表目錄
表3.1 測試樣本結構定義…….…………………………………………………18
表3.2 翹曲形狀定義….........................…………………………………………19
表3.3 Molding Compound 1 材料選擇….....................................................……23
表3.4 封裝產品資訊模擬條件.........................................................……………23
表3.5 玻璃載體條件.........................................................................................…24
表3.6 Molding Compound 2 材料選擇.............................................................…25
表3.7 封裝產品資訊模擬條件.........................................................................…25
表3.8 玻璃載體模擬條件資訊.........................................................................…26
表3.9 溫度量測點.............................................................................................…30
表4.1 可靠度條件規範.....................................................................................…44


圖目錄
圖1.1 全球半導體市場…................................................………………………...1
圖1.2 台灣IC產業產值...................................................………………………...2
圖1.3 先進封裝產品市場動態………...…………………………………………3
圖1.4 2.5D封裝示意圖…........................................………………………………4
圖1.5 2.5D封裝製程示意圖…........………………………………………………5
圖1.6 FO-EB封裝示意圖…………………………………………………………8
圖2.1 晶片與導線架透過金屬線導通示意圖…………………………………10
圖2.2 導線架打線接合產品示意圖.........………………………………………11
圖2.3 基板打線接合產品示意圖.............………………………………………11
圖2.4 打線封裝流程示意圖…...............………………………………………12
圖2.5 覆晶封裝示意圖…………………………………………………………13
圖2.6 覆晶產品封裝流程圖-FCCSP……………………………………………14
圖2.7 覆晶產品封裝流程圖-FCBGA………..…………………………………15
圖2.8 系統級封裝流程圖……….........…………………………………………16
圖2.9 先進封裝流程圖.........................................………………………………17
圖3.1 模組結構示意圖….........…………………………………………………19
圖3.2 2.5D與FO-EB模組翹曲模擬結果.………………………………………20
圖3.3 2.5D與FO-EB封裝翹曲模擬結果.………………………………………20
圖3.4 FO-EB封裝流程示意圖…..........…………………………………………22
圖3.5 FO-EB Molding 1模擬結果示意圖…............................…………………24
圖3.6 FO-EB Molding 2模擬結果示意圖........…………………………………26
圖3.7 FO-EB 玻璃載體模擬結果示意圖.……………………………………27
圖3.8 光柵示意圖.........................................……………………………………28
圖3.9 疊紋示意圖.........................................……………………………………29
圖3.10 陰影疊紋法系統示意圖...................……………………………………29
圖3.11 測試樣本量測示意圖.......................……………………………………30
圖4.1 陰影疊紋法量測結果(Sample 1)…………………………………………32
圖4.2 陰影疊紋法量測結果(Sample 2)…….............…………………………36
圖4.3 陰影疊紋法量測結果….…………………………………………………40
圖4.4 2.5D與FO-EB陰影疊紋法量測比較結果(模組).......……………………42
圖4.5 2.5D與FO-EB陰影疊紋法量測比較結果(封裝成品)…...………………43
圖4.6 SAT掃描結果...............................…………………………………………44
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