臺灣博碩士論文加值系統

本論文擬實現一個具製程、溫度補償技巧六十億赫茲展頻時脈產生器，並採用三角波展頻技術。在相同功耗下實現多相位時脈產生器，將面臨操作頻率之上限，在此提供次環提升頻率，為了實現低功耗使用製程補償技術(GPC)，此技術也可以提高良率。展頻功能透過具製程溫度補償的高速八對二類比式多工器，降低受製程溫度變異而影響以及頻率影響，使除數更加準確，藉此能擁有更佳的展頻效能，在比較三角波、洋蔥波以及亂數波三種情況下，使用一階三角調變器來實現展頻時脈產生器，即可達到相當優異且平坦度高的電磁干擾抑制效果。除此之外，電路加上了偵測VC+/-的多頻帶控制電路來調電壓控制振盪器尾電流的方式實現對製程、溫度、操作電壓變異低靈敏度且低KVCO的展頻時脈產生器，而對電磁干擾抑制效果有更進一步改善。
本論文的測試晶片實現於台積電90nm製程(1P9M)，核心電路的面積為0.015 mm2。本論文使用的電壓源為1V，輸出時脈的基礎頻率為6GHz，核心電路之總功耗為6.3mW，電磁干擾抑制能力則為約23dB。成功實現了低功耗並有良好電磁干擾抑制能力的展頻時脈產生器。

In this thesis, a 6Gbit/s fully differential spread spectrum clock generator is realized by using the process compensation scheme and triangular wave modulation.
Implementing multiple bit clock generators under the same power consumption will face the upper limit of the operating frequency. Sub-feedback loop technique is added to increase the frequency. In order to achieve high yield chip, the Gate−controlled Process Compensator is used. This technique can reduce process error and power consumption. The spread spectrum function uses a high-speed 8 to 2 analog multiplexers with GPC, it makes phase switching more accurate, there by enabling better spread spectrum performance. Comparing the triangular wave, onion wave and random number wave, using the triangular modulator to realize the spread spectrum clock generator can achieve a good and flat electromagnetic interference suppression effect.
In addition, the circuit adds a multi-band control circuit that detects VC+/- to regulate the tail current of the voltage-controlled oscillator to realize a spread-spectrum clock generator with low sensitivity to process, temperature, and operating voltage variations.
The test chip in this thesis is implemented in TSMC's 90nm process (1P9M), and the area of the core circuit is 0.015 mm2. The voltage source used in this paper is 1V, the operation frequency is 6GHz, the total power consumption of the core circuit is 6.45mW, and the EMI redution is around 23dB. Successfully implemented a spread spectrum clock generator with low power consumption and good EMI suppression capability.

誌 謝 II
國立臺北大學電機工程學系 111 學年度第 2 學期碩士學位論文提要 III
論文題目：使用八相位調變之六十億赫茲展頻時脈產生器 III
論文頁數：99頁 III
ABSTRACT IV
目 錄 V
圖 目 錄 VII
表 目 錄 XI
第1章 緒 論 1
1-1 研究動機與目的 1
1-2 論文章節架構 4
第2章 先前技術探討 5
2-1 展頻時脈概念 5
2-2 基本鎖相迴路 9
2-3 三角積分調變技術 11
2-4 相位切換研究 17
2-5 多頻帶校正技術與相關先前研究 21
2-6 次環回授壓控振盪器 22
2-7 小結 23
第3章 展頻時脈產生器電路設計 24
3-1 本論文設計概觀 24
3-2 頻率選擇器 ( Frequency selector) 26
3-3 相位頻率偵測器 ( Phase Frequency Detector ) 26
3-4 全差動式電荷泵 ( Differential Charge Pump with CMFB ) 33
3-5 迴路濾波器 ( Low Pass Filter, LPF) 42
3-6 八相位折疊式差動壓控振盪器 ( 8 phase Folded Differential VCO ) 48
3-7 多頻帶校正電路 ( Multi-band VCO Calibration ) 57
3-8 高速8對2多工器(CML 8 to 2 multiplexer) 60
3-9 預除器 ( prescaler ) 62
3-10除頻器 ( Divider ) 64
3-11 一階三角積分調變器 ( 1st-order Δ-Σ Modulator ) 65
3-12三角波產生器 ( Triangle Wave Generator ) 68
3-13 相位選擇器( Phase Selector) 72
3-14 全電路功率消耗 73
3-15 行為模擬(Behavior Simulation) 75
第4章 電路佈局模擬 77
4-1 展頻時脈展生器電路佈局 77
4-2 展頻時脈產生器佈局前和佈局後模擬比較 83
4-3 參考突波在展頻範圍內 88
4-4 文獻比較 91
4-5 晶片量測規劃 93
第5章 結論與未來研究方向 95
5-1結論 95
5-2未來研究方向 95
參考文獻 96
著作權聲明 100

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