臺灣博碩士論文加值系統

隨著科技不斷進步，物聯網的興起將大幅改變人類的生活方式，而如此方便的技術是建立在大量設置於生活環境中的感測器不間斷地收集環境資訊並回傳資料，然而電力供給成為實現這項技術的最大障礙，若使用傳統電池供電其人力維護與環境汙染成本過高，在實際應用上不符合經濟效益，因此便有環境能量擷取的相關研究出現，透過直接於環境中收集能量後轉換成電能供感測器終端使用。本論文以振動能轉電能為研究主題，使用自製壓電元件，透過正壓電效應收集電能，並經相關處理後供感測器驅動。
受振動的壓電元件透過正壓電效應所產生的能量為交流電源，所以實際應用時，需透過介面電路進行整流後才可供一般電路使用，因此傳統以二極體組成的全橋整流器作為壓電元件的介面電路，然而因二極體能量損耗過大造成轉換效率過差，因此開始有許多相關研究提出不同的介面電路架構，透過非線性開關切換，以提高系統轉換效率。但在提升介面電路效率的同時，其架構與控制電路的複雜度也隨之提升，造成能量擷取系統本身也需不小的電能消耗，導致實現「自供電」目標成為介面電路架構中不易達成的目標。
本論文將著重於研究介面電路中最難實現自供電系統的同步切換架構，首先針對不同的介面電路架構進行介紹與分析，並說明本論文選擇電感並聯式同步切換介面電路作為實現自供電系統的原因，接著透過兩版以TSMC 0.18μm高壓CMOS製程實現之晶片驗證所提出之自供電系統。本論文先後結合自行設計之主動式二極體、具正回授機制之CMOS比較器、電壓偵測器、帶差參考電路、閘極反摻雜參考電壓電路、自供電型延遲訊號產生器、脈衝產生器、起停式控制…等其他相關電路，在第一版晶片中成功驗證功率級電路之可能性，並於第二版晶片實現在不需外部供電與參考電壓的情況下，可自主運行之自供電同步切換介面電路，同時高度整合控制電路，使外部元件僅需壓電元件、儲能電容與電感便可正常運作，並可透過數位腳位切換進行控制訊號之精準微調。經佈局後模擬顯示在壓電元件等效電流源振幅為13μA、頻率為80Hz、寄生電容為14.45nF下，電壓翻轉效率達92.48%，且壓電元件輸出功率高達37.66μW，同時控制電路最大功耗僅8.87μW，且系統可在不同製程變異與大範圍溫差下維持正常運作，充分驗證晶片之可靠度。

With the continuous advancement of technology, the rise of the Internet of Things (IoT) will significantly change human lifestyles. Such convenient technology is built on a large number of sensors installed in the living environment that continuously collect environmental information and return data. However, the power supply has become the biggest obstacle to achieving this technology. If traditional batteries are used, the cost of human maintenance and environmental pollution is too high, which is not cost-effective in practical applications. Therefore, research related to environmental energy harvesting has emerged, which collects energy directly from the environment and converts it into electrical energy for use by sensor terminals. This thesis focuses on the topic of vibration energy conversion into electrical energy, using self-made piezoelectric energy harvester(PEH) to collect electrical energy through the positive piezoelectric effect and provide power to sensors after relevant processing.
The energy generated by the PEH subjected to vibration through the positive piezoelectric effect is an AC power source. Therefore, rectification through an interface circuit is required before it can be used by a general circuit in practical applications. Traditional full-bridge rectifiers composed of diodes have been used as the interface circuit for PEH. However, due to the significant energy loss of diodes, the conversion efficiency is poor, so many related studies have proposed different interface circuit structures, which use nonlinear switches to improve system conversion efficiency. Although improving the efficiency of the interface circuit can enhance the energy conversion performance, it also increases the complexity of the circuit structure and control, resulting in a significant energy consumption by the energy harvesting system. As a result, achieving the goal of "self-powered" becomes challenging in the interface circuit architecture.
This thesis focuses on researching the synchronized switch harvesting interface circuit, which is the most difficult to implement self-powered architecture. Firstly, different kinds of interface circuit are introduced and analyzed, and the reason why this thesis chooses parallel rectifier based on synchronized switch harvesting on with inductor(P-SSHI) to achieve the self-powered system is explained. Next, the proposed self-powered system is verified using two versions of chips implemented with TSMC 0.18μm High Voltage CMOS process. This thesis combines self-designed active diodes, CMOS comparators with positive feedback mechanism, voltage detectors, bandgap reference, flipped-gate voltage reference, self-powered delay signal generators, pulse generators, bang-bang controls, and other related circuits to successfully verify the feasibility of power-level circuits in the first version of the chip. In the second version of the chip, a self-powered synchronized switch harvesting interface circuit that can run independently without external power supply and reference voltage is achieved, and the control circuit is highly integrated. Only PEH, energy storage capacitors, and inductors are needed to operate normally, and the control signal can be finely adjusted through digital pins. According to post-layout simulation result, the bias-flip efficiency reaches 92.48% under an equivalent current source amplitude of 13μA, a frequency of 80Hz, and a parasitic capacitance of 14.45nF. The output power of the PEH is up to 37.66μW, while the maximum power consumption of the control circuit is only 8.87μW. The system can also maintain normal operation under different process variations and a wide range of temperature differences, fully verifying the reliability of the chip.

致謝 I
中文摘要 III
Abstract V
目錄 VII
圖目錄 X
表目錄 XIV
第1章 緒論 1
1.1 研究動機 1
1.2 文獻回顧 2
1.3 論文架構 4
第2章 壓電能量擷取系統 5
2.1 壓電效應與壓電材料 5
2.2 壓電能量擷取器 7
2.3 壓電元件等效電路模型 9
第3章 壓電能量擷取介面電路 13
3.1 標準能量擷取介面電路 13
3.2 電感並聯式同部切換介面電路 17
3.3 同步電荷擷取介面電路 20
3.4 同步電壓反轉與電荷擷取介面電路 23
3.5 介面電路比較與討論 27
第4章 自供電型電感並聯式同步切換介面電路 29
4.1 電路目標與設計考量 29
4.2 電路架構 30
4.3 第一版晶片介紹 30
4.3.1 子電路設計 30
-1 負電壓轉換器 30
-2 電壓翻轉開關與驅動電路 33
-3 主動式二極體 34
-4 高速比較器 37
-5 第一版帶差參考電路 39
-6 自供電型可調式延遲訊號產生器 41
-7 電壓翻轉控制電路 43
-8 電壓偵測電路 45
-9 第一版系統喚起電路 48
4.3.2 全晶片模擬結果 49
4.3.3 第一版晶片佈局與腳位介紹 52
4.3.4 第一版晶片量測架設 54
4.3.5 量測結果與討論 55
4.4 第二版晶片介紹 62
4.4.1 子電路設計 62
-1 無電阻自供電型主動式二極體 62
-2 第二版帶差參考電路 66
-3 脈衝產生器 71
-4 第二版系統喚起電路 75
4.4.2 第二版晶片系統架構與實驗架設 77
4.4.3 晶片佈局 81
4.4.4 模擬結果 83
第5章 結論與未來展望 87
5.1 結論 87
5.2 未來展望 87
參考文獻 89

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