臺灣博碩士論文加值系統

本論文所提及的SHA512-256d演算法為Radiant區塊鏈的演算法，區塊鏈是一種分散式的資料庫，可以儲存各種交易和資訊，而且不需要中央機構來驗證或管理，不受政府或銀行的控制。其中最為有名的區塊鏈是比特幣，其發明者是一位化名為中本聰的人物，他在2008年發表了一篇論文，介紹了比特幣的設計原理和運作方式。本論文所提及的Radiant改良自比特幣，將比特幣使用的SHA256演算法更進為SHA512-256d演算法，來提供一種安全、透明和更加去中心化的方式來進行網路交易。
Radiant使用工作量證明機制(Proof of Work)，工作量證明透過消耗大量硬體資源、電力、時間來解碼一個複雜的數學問題，成功解碼的人才能創建新的區塊，並獲得獎勵。為了維持這個機制，必須操作SHA512-256d演算法並得到小於特定值的答案，其中單位時間內的計算次數則稱為算力(hash rate)，而論文內容將會針對如何提升SHA512-256d演算法的算力來討論，並以FPGA實作。
SHA512-256d演算法的特性是compute-bound和compute-hard，也就是會需要大量運算資源和暫存器，其目的是為了要防止ASIC以及FPGA利用硬體高運算效率的特性，導致算力被主宰。SHA512-256d演算法將SHA512演算法輸入兩次，並返回前256位作為輸出。相較比特幣使用的SHA256演算法，這種方法可以提高安全性，提升了用來計算的資料寬度，而這也導致ASIC及FPGA面積的使用大大提升，成本也隨之上升，使ASIC及FPGA無法完美發揮其運算快速之優勢。儘管如此，本論文仍將利用現有FPGA的有限資源進行分析及實作。
本論文將SHA512-256d演算法實作於Xilinx FPGA VU33P晶片上，並使用Xilinx的開發軟體Vivado進行synthesis、routing和routing，藉由分析原版SHA512-256d演算法缺點，將架構加以改良，使算力能進一步提升。論文中詳述SHA512-256d演算法分析、原版硬體架構缺點之分析、演算法新硬體架構設計、FPGA硬體資源整理分配、最後實作以及在FPGA進行emulation的結果。論文最後整理出了原版及新版架構的算力差距、資源使用，以及新版emulation的結果。

The SHA512-256d algorithm discussed in this thesis is the algorithm used by the blockchain Radiant. Blockchain is a decentralized database that can store various transactions and information without the need for a central authority to verify or manage it, making it independent of governments or banks. The most famous blockchain is Bitcoin, which was introduced in a paper by an anonymous person or group named Satoshi Nakamoto in 2008, explaining the design principles and operation of Bitcoin. Instead of using the SHA256 algorithm employed by Bitcoin, Radiant utilizes the SHA512-256d algorithm. This enhancement aims to provide a more secure, transparent, and decentralized way of conducting network transactions.
Radiant utilizes Proof of Work, in which participants significant hardware resources, electricity, and time to solve a complex mathematical problem, and only those who successfully solve the problem can create new blocks and receive rewards. To maintain this mechanism, the SHA512-256d algorithm is operated, and the goal is to obtain an answer that is less than a specific value. The number of calculations performed per unit of time is referred to as the hash rate, and the paper discusses how to enhance the hash rate of the SHA512-256d algorithm, specifically through FPGA implementation.
The SHA512-256d algorithm is characterized as compute-hard, meaning it requires a significant amount of computational resources and registers to prevent ASIC and FPGA devices from dominating the hashing power by their hardware efficiency. The SHA512-256d algorithm takes the SHA512 algorithm as input twice and returns the first 256 bits as the output. This approach, compared to the SHA256 algorithm used in Bitcoin, enhances security by increasing the data width used for computation. However, this also leads to a significant increase in the utilization and cost of ASIC and FPGA resources, limiting their ability to fully exploit their computational speed advantages. Nonetheless, this paper will analyze and implement the algorithm using the limited resources of existing FPGAs.
This paper implements the SHA512-256d algorithm on the Xilinx FPGA VU33P chip using Xilinx's development software, Vivado, for synthesis, routing, and placement. By analyzing the drawbacks of the original SHA512-256d algorithm, the architecture is improved to further enhance the hash rate. The paper provides a detailed analysis of the SHA512-256d algorithm, an analysis of the drawbacks of the original hardware architecture, the design of the new hardware architecture for the algorithm, allocation of FPGA hardware resources, implementation details, and the results of emulation on the FPGA. The paper concludes by presenting the difference in hash rates and resource utilization between the original and new architectures, as well as the results of the new architecture's emulation on the FPGA.

口試委員會審定書 i
學位論文學術倫理暨原創性聲明書 ii
摘要 iii
Abstract v
Contents vii
List of Figures x
Figures of Chapter 2 x
Figures of Chapter 3 x
List of Tables xiii
Tables of Chapter 2 xiii
Tables of Chapter 3 xiii
Tables of Chapter 4 xiv
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Organization of the Thesis 3
Chapter 2 Preliminary and the problems of original architecture 4
2.1 Introduction to Hash function and Radiant 4
2.2 The property of SHA512-256d algorithm 5
2.2.1 Overview of SHA512-256d algorithm 5
2.2.2 Software design of SHA512-256d functions 7
2.3 Problem Statement 9
2.3.1 Introduction of FPGA VU33P 10
2.3.2 Original hardware architecture 11
Chapter 3 Circuit Improvement of SHA512-256d Algorithm 14
3.1 Design methodologies on FPGA 14
3.2 Design strategy and constraints 15
3.3 Analysis of Round function 16
3.4 New architecture of Round function 17
3.4.1 Pipeline method in Round function 17
3.4.2 Precompute in Transform_func of E variable 18
3.4.3 Precompute in Transform_func of A variable 22
3.5 Building architecture for Message_scheduler 25
3.5.1 Two-stage pipelined of Message_scheduler 25
3.5.2 New architecture for Message_scheduler 28
3.5.3 Discussion of the resource distribution in the Message_scheduler module 31
3.6 Block building of SHA512-256d 34
3.7 Overview of the whole system 38
3.7.1 The overview of the design on FPGA 38
3.7.2 Ncefifo_top 40
Chapter 4 Measurement result 43
Chapter 5 Future work 48
5.1 Review 48
5.2 Future work 48
Reference 50
Appendix 53
A.1 80 constants Ki for each SHA512-256 operations 53
A.2 The number of registers required to delay each of the 64 Word_i inputs in the Word_SRL module 54

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