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研究生:羅奧文
研究生(外文):Arvind Singh Rathore
論文名稱:利用突變分析認證功能驗證環境以增強基於模擬的驗證流程
論文名稱(外文):Enhancing Simulation-Based Verification Flow by Mutation-Analysis Driven Qualification of Functional Verification Environment
指導教授:黃鐘揚
指導教授(外文):Chung-Yang Huang
口試委員:文啟能李建模黃紹倫莊咸和
口試委員(外文):Dave WenChien-Mo LiShao-Lun HuangHsien-Ho Chuang
口試日期:2023-07-24
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電子工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2023
畢業學年度:111
論文頁數:60
中文關鍵詞:順序等價性檢查突變覆蓋率測試平台品質改善突變體錯誤驗證環境
外文關鍵詞:Sequential Equivalence CheckingMutation CoverageTestbench QualificationMutation-AnalysisFaultVerification Environment
DOI:10.6342/NTU202303654
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  • 點閱點閱:20
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由於集成電路的複雜性呈指數增長,功能驗證已成為IC設計驗證流程的重要部分。功能驗證的困難隨著市場競爭日趨激烈、產品上市時間的壓力而增加。這些挑戰需要使用高質量的測試平臺,才能夠徹底驗證設計。而要找出一個錯誤,測試平台必須模擬各種可能性,將錯誤行為傳播到一些檢查點,並在這些檢查點使用檢查器進行觀測。在主要的驗證方法中,一般人會採用覆蓋率指標評估測試平台,例如代碼覆蓋率和功能覆蓋率。然而,這些指標主要關注錯誤的激活,而忽視了錯誤的傳播和檢測階段,這可能導致一些錯誤未被檢測,而對系統構成潛在的風險。所以完整的驗證流程需要一個額外的指標,稱之為突變覆蓋率,來補充現有的指標並解決這些驗證差距。這篇論文提出了一種方法,使用突變覆蓋率的反饋來改進基於模擬的功能驗證,從而提高驗證環境(VE)的質量。我們在一個已經具有成熟驗證的複雜設計上進行實驗,結果顯示即使在這個驗證已經相對完整的設計上,我還們是可以持續地將驗證質量大幅提升,並且同時揭示了現有驗證環境中的幾個漏洞。
Functional verification has become an integral part of the IC design verification flow due to the exponential growth in the size and complexity of integrated circuits. The difficulty of functional verification increases in tandem with the mounting pressure to swiftly release products amidst intense market competition. Due of the aforementioned challenges, a top-notch testbench that can completely verify the design is required. A bug must be stimulated, propagated to some checked sites, and then detected there using checkers for the testbench to reveal it. In common verification methodologies, the success of the test vectors produced by the testbench is assessed using coverage metrics, specifically code coverage and functional coverage. These metrics, however, mainly focus on bug activation, leaving significant gaps in addressing propagation and detection stages. These gaps could result in undetected bugs, posing potential system risks. An additional metric, called mutation coverage, is needed to complement the existing metrics and address these verification gaps. This thesis proposes a methodology to improve simulation-based functional verification using mutation coverage feedback, thereby enhancing the quality of the verification environment (VE). Experimental results on a complex digital design with mature verification efforts demonstrate substantial quality improvement and reveal several vulnerabilities in the existing verification environment.
Acknowledgement i
中文摘要 ii
ABSTRACT iii
CONTENTS iv
LIST OF FIGURES vi
LIST OF TABLES viii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Related Work 4
1.3 Contributions 7
1.4 Thesis Organization 8
Chapter 2 Background Knowledge 9
2.1 Terminology Definitions 9
2.2 Coverage Metrics 11
2.3 Functional Qualification 15
2.4 Mutation Analysis 16
2.5 Mutation Types 18
2.6 Problem of Equivalent Mutations 22
2.7 Equivalence Checking 24
Chapter 3 Overview of Mutation Analysis Framework 26
3.1 The Architecture of Our Framework 26
3.2 Mutation Creation 29
3.3 Storage Strategy 31
3.4 Mutation Filtering 33
3.5 Mutation Coverage 34
3.6 Mutation Analysis 37
3.7 Verification Environment Improvement 40
Chapter 4 Experimental Results 42
4.1 A Brief Overview of the Design Under Verification 42
4.2 Testbench Architecture 44
4.3 Test-Suite 46
4.4 Experimental Findings 47
4.5 Results 54
Chapter 5 Conclusions and Future Work 55
5.1 Integration Efforts 55
5.2 Conclusion 56
5.3 Future Work 57
REFERENCES 58
[1] Erwinkarim, “M1 Pro vs M1 Max: Is It Worth It?,” Tech Journeyman. https://techjourneyman.com/blog/m1-pro-vs-m1-max-is-it-worth-it/
[2] L. Collins, “Using sequential equivalence to verify clock-gating strategies - Tech Design Forum Techniques,” Tech Design Forum Techniques, Mar. 31, 2019. https://www.techdesignforums.com/practice/technique/using-sequential-equivalence-to-verify-clock-gating-strategies/
[3] “VC Formal: Formal Verification Solution | Synopsys Verification.” https://www.synopsys.com/verification/static-and-formal-verification/vc-formal.html
[4] “Ibex RISC-V Core,” GitHub, Dec. 09, 2022. https://github.com/lowRISC/ibex
[5] “Google RISCV-DV” GitHub, Aug. 08, 2023. https://github.com/chipsalliance/riscv-dv
[6] K. Huang, P. Zhu, R. Yan, and X. Yan, “Functional Testbench Qualification by Mutation Analysis,” VLSI Design, vol. 2015, pp. 1–9, May 2015, doi: https://doi.org/10.1155/2015/256474.
[7] V. Guarnieri et al., “On the Reuse of TLM Mutation Analysis at RTL,” Journal of Electronic Testing, May 2012, doi: https://doi.org/10.1007/s10836-012-5303-6.
[8] N. Bombieri et al., “HIFSuite: Tools for HDL Code Conversion and Manipulation,” EURASIP Journal on Embedded Systems, vol. 2010, no. 1, pp. 436328–436328, Jan. 2010, doi: https://doi.org/10.1155/2010/436328.
[9] Serrestou, Beroulle, and Robach, “Functional Verification of RTL Designs driven by Mutation Testing metrics,” HAL (Le Centre pour la Communication Scientifique Directe), Aug. 2007, doi: https://doi.org/10.1109/dsd.2007.4341472.
[10] T. Xie, W. Mueller, and Florian Letombe, “HDL-Mutation Based Simulation Data Generation by Propagation Guided Search,” Aug. 2011, doi: https://doi.org/10.1109/dsd.2011.83.
[11] T. Xie, W. Mueller, and Florian Letombe, “Mutation-analysis driven functional verification of a soft microprocessor,” Sep. 2012, doi: https://doi.org/10.1109/socc.2012.6398362.
[12] Y. Jia and M. Harman, “An Analysis and Survey of the Development of Mutation Testing,” IEEE Transactions on Software Engineering, vol. 37, no. 5, pp. 649–678, Sep. 2011, doi: https://doi.org/10.1109/tse.2010.62.
[13] “PIT Mutation Testing,” pitest.org. https://pitest.org/
[14] "Stryker Mutator: Test your tests with mutation testing”. https://stryker-mutator.io/
[15] “PHP Mutation Testing Framework.” https://infection.github.io/
[16] “Mutate++ - A C++ Mutation Test Environment” https://github.com/nlohmann/mutate_cpp
[17] N. Bombieri, Franco Fummi, and Graziano Pravadelli, “A mutation model for the SystemC TLM 2.0 communication interfaces,” Mar. 2008, doi: https://doi.org/10.1145/1403375.1403472.
[18] P. Lisherness and K.-T. Cheng, “Improving validation coverage metrics to account for limited observability,” Jan. 2012, doi: https://doi.org/10.1109/aspdac.2012.6164962.
[19] P. Lisherness, N. Lesperance, and K.-T. Cheng, “Mutation Analysis with Coverage Discounting,” Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013, Jan. 2013, doi: 10.7873/date.2013.021.
[20] P. Lisherness and K.-T. Cheng, “Coverage discounting: A generalized approach for testbench qualification,” Nov. 2011, doi: https://doi.org/10.1109/hldvt.2011.6114165.
[21] F. Fallah, Srinivas Devadas, and K. Keutzer, “OCCOM-efficient computation of observability-based code coverage metrics for functional verification,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 8, pp. 1003–1015, Jan. 2001, doi: https://doi.org/10.1109/43.936381.
[22] Tao Lv, J. Fan, X. Li, and L.-Y. Liu, “Observability Statement Coverage Based on Dynamic Factored Use-Definition Chains for Functional Verification,” Journal of Electronic Testing, vol. 22, no. 3, pp. 273–285, Jun. 2006, doi: https://doi.org/10.1007/s10836-006-8634-3.
[23] "Cetress Certitude" http://www.certess.com/product/2006
[24] “Testbench Quality Assurance | Synopsys,” www.synopsys.com. https://www.synopsys.com/verification/simulation/testbench-quality-assurance.html
[25] "Mutation Cover with Yosys." YosysHQ. https://github.com/YosysHQ/mcy
[26] A. T. Acree, T. A. Budd, R. A. De- Millo, R. J. Lipton, and F. G. Sayward. Mutation analysis. Technical report GIT-ICS-79/08, School of Information and Computer Science, Georgia Institute of Technology, Atlanta GA, September 1979.
[27] R. A. DeMillo, R. J. Lipton, and F. G. Sayward. Hints on test data selection: Help for the practicing programmer. Computer, 11(4), April 1978.
[28] “Synopsys Design Compiler” https://www.synopsys.com/implementation-and-signoff/rtl-synthesis-test/dc-ultra.html
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