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研究生:李愷
研究生(外文):Kai Li
論文名稱:於DDR模組中多條耦合線的快速眼圖指標解析法
論文名稱(外文):Analytic Method of Fast Eye-diagram Index for Multiple Coupled Lines in DDR
指導教授:吳瑞北
指導教授(外文):Ruey-Beei Wu
口試委員:郭維德周求致李建銘陳永裕
口試委員(外文):Wei-Da GuoChiu-Chih ChouChien-Ming LeeYung-Yu Chen
口試日期:2023-07-25
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電信工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2023
畢業學年度:111
語文別:中文
論文頁數:69
中文關鍵詞:信號完整性串擾轉移函數快速眼圖指標脈波響應眼圖峰值失真分析
外文關鍵詞:signal integritycrosstalktransfer functionfast eye-diagram indexsingle bit responseeye diagrampeak distortion analysis
DOI:10.6342/NTU202302290
相關次數:
  • 被引用被引用:1
  • 點閱點閱:295
  • 評分評分:
  • 下載下載:54
  • 收藏至我的研究室書目清單書目收藏:1
DDR技術隨著科技進步不斷發展,越來越多的電子產品採用DDR技術來實現高速數據傳輸,高速DDR傳輸所涉及的信號完整性問題也越來越重要。在DDR設計中,需要考慮信號的傳輸延遲、反射、串擾等因素對信號完整性的影響,本文探討了在不匹配邊界條件下,通過推導單一傳輸線的轉移函數,進而推廣出多條耦合傳輸線之間的轉移函數,再利用反向傅立葉變換可以獲得其脈波響應,並基於峰值失真分析的方式,可以快速地獲取眼圖高度和寬度。相比使用正反相偽隨機二進位序列(PRBS)分析眼圖的做法,本法可以節省約15000倍的時間,並相較最劣眼圖的眼高誤差改善可高達12倍。
DDR technology has been continuously developing with the advancement of technology, and an increasing number of electronic products are adopting DDR technology to achieve high-speed data transmission. The signal integrity issues involved in high-speed DDR transmission are becoming increasingly important. In DDR design, factors such as signal propagation delay, reflection, and crosstalk need to be considered for signal integrity. This paper discusses the derivation of the transfer function of a single transmission line under mismatched boundary conditions and extends it to the transfer function between multiple coupled transmission lines. By utilizing inverse Fourier transform, we obtains the pulse response and, based on peak distortion analysis, quickly obtains the height and width of an eye diagram. Compared to the method of analyzing eye diagrams using pseudo-random binary sequence (PRBS), this approach saves approximately 15000 times the time and can improve the eye height error of the worst eye diagram by up to 12 times.
口試委員會審定書 i
誌謝 ii
中文摘要 iii
ABSTRACT iv
CONTENTS v
圖目錄 vii
表目錄 x
Chapter 1 緒論 1
1.1 研究動機 1
1.2 文獻回顧 2
1.3 主要貢獻 4
1.4 章節內容概述 4
Chapter 2 理論背景 5
2.1 DDR模組介紹 5
2.1.1 DDR的原理及特性 5
2.1.2 DDR的傳輸路徑 6
2.1.3 On-Die Termination 7
2.2 眼圖原理及介紹 9
2.2.1 眼圖形成的原理 9
2.2.2 偽隨機二進位序列(Pseudorandom Binary Sequence, PRBS)信號 10
2.3 基於脈波響應的峰值失真分析 11
2.3.1 線性非時變(Linear Time-Invariant System, LTI)系統 11
2.3.2 脈波響應(Pulse Response) 12
2.3.3 符碼間干擾(Inter Symbol Interference, ISI) 16
2.3.4 眼圖最劣序列(Worst-case Bit Pattern) 18
Chapter 3 快速眼圖指標解析法 19
3.1 眼圖指標 19
3.2 單一傳輸線的轉移函數 23
3.3 多條耦合線的轉移函數 26
3.4 帶有並聯電路邊界的轉移函數 30
Chapter 4 DDR4電路眼圖指標分析 32
4.1 DDR4電路介紹 32
4.2 S參數前處理及包含時鐘訊號的峰值失真分析 35
4.2.1 S參數前處理 35
4.2.2 包含時鐘訊號的峰值失真分析 40
4.3 眼圖指標分析 41
4.3.1 解析法與正反相偽隨機序列之眼圖比較 43
4.3.2 解析法與修正節點分析法(Modified Nodal Analysis, MNA)比較 47
Chapter 5 解析法之程式 51
5.1 程式介紹 - 問題描述及I/O設計 51
5.2 程式外觀及使用手冊 52
5.2.1 程式外觀 52
5.2.2 使用手冊 55
5.3 額外功能及注意事項 65
5.3.1 額外功能 65
5.3.2 注意事項 66
Chapter 6 結論及未來展望 67
6.1 結論 67
6.2 未來展望 67
參考文獻 68
JEDEC DDR5 SDRAM [Online]. Available: https://www.jedec.org/standards-documents/docs/jesd79-5b
R. Shi, W. Yu, Y. Zhu, C. -K. Cheng, and E. S. Kuh, "Efficient and accurate eye diagram prediction for high speed signaling," in 2008 IEEE/ACM Int. Conf. Computer-Aided Design, San Jose, CA, USA, 2008, pp. 655-661
B. K. Casper, M. Haycock, and R. Mooney, "An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling schemes," in 2002 Symp. VLSI Cir. (Cat. No.02CH37302), Honolulu, HI, USA, 2002, pp. 54-57
J. Zhang, X. Zhang, and J. Ma, "Simulation design of system-level power integrity and signal integrity of vehicle chip DDR," in 2022 Asia-Pacific Int. Symp. Electromagn. Compat. (APEMC), Beijing, China, 2022, pp. 509-511
T. Kato, S. Yamamoto, T. Sudo, Y. Ono, E. Takahashi, and T. Yamada, "Signal integrity characterization of high-speed DDR interface," in 2011 IEEE Electr. Design Adv. Packag. Syst. Symp. (EDAPS), Hanzhou, China, 2011, pp. 1-4
K.-I. Oh, L.-S. Kim, K.-I. Park, Y.-H. Jun, and K. Kim, "A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression scheme," in 2008 IEEE Custom Integrated Cir. Conf., San Jose, CA, 2008, pp. 639-642
P.-Y. Weng, C.-H. Cheng, T.-L. Wu, C.-H. Chen, J. Chen, E. Kuo, C.-L. Liao, and B. Mutnury, "Enhanced power and signal integrity through layout optimization of high-speed memory systems," in 2019 Electr. Design Adv. Packag. Syst. (EDAPS), Kaohsiung, Taiwan, 2019, pp. 1-3
S.-Y. Huang, Y.-S. Cheng, K.-Y. Yang, and R.-B. Wu, "Fast prediction and optimal design for eye-height performance of mismatched transmission lines," IEEE Trans. Compon., Packag. Manuf. Technol., vol. 4, no. 5, pp. 896-904
K. Scharff, H.-D. Brüns, and C. Schuster, "Efficient crosstalk analysis of differential links on printed circuit boards up to 100 GHz," IEEE Trans. Electromagn. Compat., vol. 61, no. 6, pp. 1849-1859, Dec. 2019
K. Scharff, H.-D. Brüns, and C. Schuster, "Performance metrics for crosstalk on printed circuit boards in frequency domain," in 2019 IEEE 23rd Workshop Signal Power Integrity (SPI), Chambéry, France, 2019, pp. 1-4
H.-H. Zou, P.-J. Ma, J.-Y. Shi, K. Li, and Z.-X. Di, "The optimization and application of DDR controller based on multi-core system," in 2012 IEEE 11th Int. Conf. Solid-State Integrated Cir. Technol., Xi'an, China, 2012, pp. 1-3
R. Wei, C. Li, C. Chen, G. Sun, and M. He, “Memory access optimization of a neural network accelerator based on memory controller,” Electron. 2021; 10(4):438.
B. Dannan, " Signal integrity characterization of via subs on high speed DDR4 channels," DesignCon, Jan. 2020.
S. N. Wong, "An algorithmic study of DDR3 SDRAM on-die termination switch timings," in 2012 IEEE Workshop Microelectron. Electron Dev., Boise, ID, USA, 2012, pp. 1-4
EFRAM. “On-die termination (ODT) / What is different between dynamic ODT and dynamic OCT when interfacing DDR3 SDRAM with Stratix III or Stratix IV FPGAs?” [Online]. Available: https://m.blog.naver.com/PostView.naver?isHttpsRedirect=true&blogId=framkang&logNo=220456911948
張瑋儒,脈衝振幅調變於高速串列解列系統中眼圖分析與等化設計,國立台灣大學碩士論文,2018年8月
Elektron. (2006). Pseudorandom binary sequence generator [Online]. Available: https://en.wikipedia.org/wiki/Pseudorandom_binary_sequence#/media/File:PRBS_15_generator.png
D. M. Pozar, Microwave Engineering. 4th ed., Wiley, 2011. (Chapter 4)
H. Lee, J. Hwang, and H. Lee, "Optimizing ODT condition and Driver's turn-on resistance to achieve SI of LPDDR dual rank configuration," in 2019 IEEE 21st Electron. Packag. Technol. Conf. (EPTC), Singapore, 2019, pp. 608-612
H.-H. Chuang, personal communication, June 1, 2023.
C.-C. Chou, personal communication, 2023.
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