臺灣博碩士論文加值系統

本論文利用TSMC提供之標準90-nm CMOS製程，研究可應用於76-81 GHz車用雷達與81-86 GHz點對點通訊系統之E頻段低雜訊放大器。論文內容分為三大部分，第一部分介紹研究動機與背景，第二部分介紹基本放大器參數以及常用架構，第三部分為兩次低雜訊放大器實作的設計流程與實際量測結果。
論文將介紹的兩次晶片實作，設計上主要考量功耗、雜訊、增益與頻寬，使用雜訊圓、增益圓與等Q圓的概念做設計。匹配網路則使用薄膜微帶線取代傳統電感與電容，佈局上須避免相鄰線之間的耦合。第一個電路設計採用四級共源級組態串接，並且各級加上源級退化電感性元件，使電晶體可以在低功耗的狀況下達到穩定並且降低雜訊指數。量測結果在81.5 GHz具有18.4 dB的峰值增益，且3 dB增益頻寬從76.5-87.5 GHz為11 GHz，而在86 GHz有最低5.0 dB的雜訊指數，整體功率消耗為14 mW，晶片面積為0.487 mm^2。第二個電路採用三級電流再利用組態串接，對訊號來說實際上可以等效為六級共源極串接，因此可以在維持高增益的狀況下改善各級貢獻的功耗。量測結果在83.5 GHz具有18.9 dB的峰值增益，且3 dB增益操作頻率從72.5-88.5 GHz，頻寬達到16.5 GHz，而在87 GHz有6.4 dB的最低雜訊指數，整體功率消耗為18 mW，晶片面積為0.487 mm^2。

This thesis uses the standard 90-nm CMOS process provided by TSMC to design the E-band low-noise amplifier (LNA) for 76-81 GHz automotive radar and 81-86 GHz point-to-point communication systems. The thesis is divided into three parts. The first part is about the motivation and background of the research. The second part is to introduce the basic amplifier parameters and various architectures. The third part presents the design flow and the experimental results of two low-noise amplifiers.
The two chips that will be introduced in this paper mainly tradeoffs of power consumption, noise, gain, and bandwidth. The concepts of noise circle, gain circle, and constant-Q lines are used for design. Instead of traditional inductors and capacitors, the matching network is implemented by the thin-film microstrip line and careful layout is needed to avoid mutual coupling between the adjacent parallel line sections. The first circuit presents the design of a four-stage LNA. Each stage used common-source (CS) architecture with source degeneration to enhance stability and reduce noise under low power consumption. The measured peak gain is 18.4 dB at 81.5 GHz and has 3-dB frequency bandwidth of 11 GHz from 76.5 to 87.5 GHz. The measured noise has a minimum value of 5.0 dB at 86 GHz. The chip has an area of 0.487 mm^2 including pads and consumes only 14 mW of DC power.
The second circuit adopts three-stage current-reused configuration, which is actually equivalent to six-stage common-source in cascade. It can improve the power consumption contributed by each stage while maintaining high gain. The measured maximum gain is 18.9 dB at 83.5 GHz and has 3-dB frequency bandwidth of 16.5 GHz from 72.5 to 88.5 GHz. The measured minimum noise is 6.4 dB at 87 GHz. The chip has an area of 0.487 mm^2 including pads and consumes only 18 mW of DC power.

中文摘要 i
Abstract ii
誌謝 iv
目錄 v
表目錄 vii
圖目錄 viii
第一章 前言 1
1.1 研究背景與動機 1
1.2 論文架構 4
第二章 基本概念及低雜訊放大器架構 5
2.1 基本概念 5
2.1.1 S參數 5
2.1.2 雜訊源與雜訊指數 6
2.1.3 非線性效應 12
2.1.4 穩定度 14
2.2 低雜訊放大器設計架構 15
2.2.1 放大級基本設計架構 15
2.2.2 低功耗設計技巧 18
2.2.3 寬頻設計技巧 21
第三章 匹配電路設計與佈局相關考量 24
3.1 匹配電路設計 24
3.1.1 被動元件高頻特性 25
3.1.2 寬頻匹配電路設計 27
3.2 佈局相關考量 30
3.2.1 偏壓電路設計與佈局 30
3.2.2 PAD與微帶線佈局考量 33
3.2.3 靜電防護考量 36
第四章 晶片量測結果與討論 37
4.1 E-band量測系統簡介 37
4.1.1 雜訊量測系統架設 38
4.1.2 大訊號量測系統架設 39
4.2 應用於E-band低雜訊低功耗放大器設計 40
4.2.1 電路設計流程 40
4.2.2 電路與佈局圖 50
4.2.3 模擬與量測結果 52
4.2.4 結果討論與模擬修正 55
4.3 應用於E-band低功耗寬頻低雜訊放大器設計 60
4.3.1 電路架構與設計 60
4.3.2 電路與佈局圖 63
4.3.3 模擬結果 65
4.3.4 模擬與量測結果討論 67
第五章 結論 71
參考文獻 72

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