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研究生:簡楷峰
研究生(外文):Jian, Kai-Fong
論文名稱:用於防範加密電路時鐘注入攻擊之偵測電路
論文名稱(外文):A Detection Circuit against Clock Glitch Attacks in Encryption Circuits
指導教授:趙昌博
指導教授(外文):Chao, Chang-Po
口試委員:張錫嘉莊愷莘趙昌博
口試委員(外文):Chang, Hsie-ChiaChuang, Kai-HsinChao, Chang-Po
口試日期:2023-06-05
學位類別:碩士
校院名稱:國立陽明交通大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2023
畢業學年度:111
語文別:英文
論文頁數:31
中文關鍵詞:故障注入攻擊旁路攻擊時鐘毛刺差別錯誤分析故障靈敏度分析
外文關鍵詞:Fault injection attackSide-channel attackClock glitchDifferential fault analysis(DFA)Fault sensitivity analysis(FSA)
相關次數:
  • 被引用被引用:0
  • 點閱點閱:102
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摘要 i
ABSTRACT ii
Table of Content iii
List of Figures iv
List of Tables vi
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Related Work 2
1.3 Goals 4
1.4 Thesis Organization 4
Chapter 2 Detection Circuit for Clock Glitches 5
2.1 Design challenges: metastability 5
2.2 The Delay Chain 6
2.3 The Coarse-Tuning Architecture 7
2.4 Issues about Coarse-Tuning Architecture 8
2.5 The Fine-Tuning Architecture 10
2.6 Clock Glitch Detection 14
Chapter 3 Chip Implementation 15
3.1 Experimental Setup 15
3.2 Experimental Result 17
3.3 Comparison 27
Chapter 4 Conclusion and Future Works 29
4.1 Conclusion 29
4.2 Future Works 29
Reference 30
[1] P. Luo and Y. Fei, "Faulty clock detection for crypto circuits against differential fault analysis attack," Cryptology ePrint Archive, 2014.
[2] P. Luo, C. Luo, and Y. Fei, "System clock and power supply cross-checking for glitch detection," Cryptology ePrint Archive, 2016.
[3] S. Song, S. G. Tell, B. Zimmer, S. S. Kudva, N. Nedovic, and C. T. Gray, "An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET Process," in 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 12-17 June 2022 2022, pp. 146-147, doi: 10.1109/VLSITechnologyandCir46769.2022.9830157.
[4] H. Igarashi, Y. Shi, M. Yanagisawa, and N. Togawa, "Concurrent faulty clock detection for crypto circuits against clock glitch based DFA," in 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 19-23 May 2013 2013, pp. 1432-1435, doi: 10.1109/ISCAS.2013.6572125.
[5] S. Endo et al., "A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 8, pp. 1429-1438, 2015, doi: 10.1109/TVLSI.2014.2339892.
[6] M. R. Muttaki, T. Zhang, M. Tehranipoor, and F. Farahmandi, "FTC: A Universal Sensor for Fault Injection Attack Detection," in 2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 27-30 June 2022 2022, pp. 117-120, doi: 10.1109/HOST54066.2022.9840177.
[7] C. T. Daniel Nemiroff, "Fault-Injection Countermeasures, Deployed at Scale," Intel, Technical Report 2022. [Online]. Available: https://www.intel.com/content/www/us/en/architecture-and-technology/hardware-shield/fault-injection-countermeasures-white-paper.html
[8] S. Bhunia and M. Tehranipoor, "Chapter 8 - Side-Channel Attacks," in Hardware Security, S. Bhunia and M. Tehranipoor Eds.: Morgan Kaufmann, 2019, pp. 193-218.
[9] R. Soares, V. Lima, R. Lellis, P. Finkenauer Jr, and V. Camargo, "Hardware Countermeasures against Power Analysis Attacks: a Survey from Past to Present," Journal of Integrated Circuits and Systems, vol. 16, no. 2, pp. 1-12, 2021.
[10] M. Tunstall, D. Mukhopadhyay, and S. Ali, "Differential fault analysis of the advanced encryption standard using a single fault," in Information Security Theory and Practice. Security and Privacy of Mobile Devices in Wireless Communication: 5th IFIP WG 11.2 International Workshop, WISTP 2011, Heraklion, Crete, Greece, June 1-3, 2011. Proceedings 5, 2011: Springer, pp. 224-233.
[11] Y. Li, K. Sakiyama, S. Gomisawa, T. Fukunaga, J. Takahashi, and K. Ohta, "Fault sensitivity analysis," in Cryptographic Hardware and Embedded Systems, CHES 2010: 12th International Workshop, Santa Barbara, USA, August 17-20, 2010. Proceedings 12, 2010: Springer, pp. 320-334.
[12] B. Ning and Q. Liu, "Modeling and Efficiency Analysis of Clock Glitch Fault Injection Attack," in 2018 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), 17-18 Dec. 2018 2018, pp. 13-18, doi: 10.1109/AsianHOST.2018.8607175.
[13] C. Deshpande, B. Yuce, N. F. Ghalaty, D. Ganta, P. Schaumont, and L. Nazhandali, "A Configurable and Lightweight Timing Monitor for Fault Attack Detection," in 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 11-13 July 2016 2016, pp. 461-466, doi: 10.1109/ISVLSI.2016.123.
[14] T. K. Michael Rohleder, Vladimir Litovtchenko, Thomas Luedeke, "Clock glitch detection circuit," Patent Appl. US13/131,349 2011. [Online]. Available: https://patents.google.com/patent/US20110317802A1/en
[15] S. S. Gujar and L. Nazhandali, "Detecting Electromagnetic Injection Attack on FPGAs Using In-situ Timing Sensors," Journal of Hardware and Systems Security, vol. 4, pp. 196-207, 2020.
[16] M. Zhang and Q. Liu, "A digital and lightweight delay-based detector against fault injection attacks," in 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021: IEEE, pp. 1-5.
[17] A. K. Uht, "Going beyond worst-case specs with TEAtime," Computer, vol. 37, no. 3, pp. 51-56, 2004, doi: 10.1109/MC.2004.1274004.
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