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研究生:清田淳也
研究生(外文):Kiyota, Junya
論文名稱:利用四異氰酸基矽烷實現用於ESL型IGZO TFT之無氫的電漿輔助化學氣相沉積二氧化矽薄膜製程
論文名稱(外文):Implementation of Hydrogen-free SiO2 Deposition by PECVD with Tetraisocyanatesilane (TICS) for Fabrication Process of ESL-type IGZO TFT
指導教授:張翼張翼引用關係
指導教授(外文):Chang, Edward Yi
口試委員:張翼吳建華冉曉雯
口試委員(外文):Chang, Edward YiWu, Janne-WhaZan, Hsiao-Wen
口試日期:2023-03-07
學位類別:碩士
校院名稱:國立陽明交通大學
系所名稱:國際半導體產業學院
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2023
畢業學年度:111
語文別:英文
論文頁數:56
中文關鍵詞:四異氰酸基矽烷ESL 型電漿增強化學氣相沉積氧化物半導體薄膜電晶體
外文關鍵詞:TetraisocyanatesilaneESL-typePECVDIGZOTFT
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以IGZO為代表的非晶透明氧化物半導體(TAOS),作為下一代高性能薄膜晶體管TFT通道材料,近十年來逐漸被顯示行業所接受。然而,TAOS 有一個重要問題,即某些氧化物成分對環境敏感並且對元件的製造製程很不穩定。特別是在用於鈍化 SiO2 層的電漿增強化學氣相沉積 (PECVD) 製程中,氧化物材料容易被還原和氫化。這種還原過程造成的損壞是不可避免的,並且會在最終顯示產品中引入顯著的電性不均勻性。
抑制氫還原的基本解決方案之一是採用四異氰酸基矽烷(Si(NCO)4,TICS)代替傳統 PECVD 中的 SiH4 的無氫 SiO2 沉積製程。本論文,我們研究了 TICS-SiO2 薄膜和包含 TICS-SiO2 作為鈍化層的氧化物 TFT 的特性。與傳統的 SiH4-SiO2 相比,TICS-SiO2 薄膜顯示出足夠高的 11.3 MV cm-1 崩潰電壓和較低的氫結合率。此外,為了了解 TICS-SiO2 沉積對氧化物材料的影響,我們研究了 TICS-SiO2/IGZO 和 SiH4-SiO2/IGZO 堆疊層的載流子濃度。發現TICS-SiO2/IGZO的載流子濃度低於~1012 cm-3的檢測極限,而SiH4-SiO2/IGZO的載流子濃度則提高到1018 cm-3。這一結果表明,無氫 TICS-SiO2 製程有效地抑制了底層氧化層中氫引起的氧化還原反應,氧化層被認為是氧化物通道中過量載流子的主要來源。通過應用 TICS-SiO2 製程,我們成功地製造了場效應遷移率超過10 cm2 V-1s-1且可靠性更高的 ESL 型 IGZO TFT。
The practical application of amorphous transparent oxide semiconductor (TAOS) typified by IGZO has been gradually embraced by the display industry as the next generation high performance thin film transistor TFT channel materials over the past decade. However, TAOS has an essential issue that certain oxide components are environment sensitive and unstable to device fabrication processes. Especially in plasma-enhanced chemical vapor deposition (PECVD) process for passivation SiO2 layer, oxide materials are easily reduced and hydrogenated. The resulting damage by such reductive process is unavoidable and can introduce significant nonuniformity of electrical properties in final display products.
One of the fundamental solutions to suppress hydrogen reduction is to adapt a hydrogen-free SiO2 deposition process using tetraisocyanatesilane (Si(NCO)4, TICS) instead of SiH4 in conventional PECVD.
In this work, properties of TICS-SiO2 films and oxide TFTs including TICS-SiO2 as the passivation layer are studied. TICS-SiO2 films show a sufficiently high break-down voltage of 11.3 MV cm-1 and lowered hydrogen incorporation compared with conventional SiH4-SiO2. Moreover, to understand the impact of TICS-SiO2 deposition on oxide materials, carrier concentrations of TICS-SiO2/IGZO and SiH4-SiO2/IGZO stacked layers are studied. It is found that the carrier concentration of TICS-SiO2/IGZO is lower than the detection limit of of ~1012 cm-3, while that of SiH4-SiO2/IGZO has been boosted to up to 1018 cm-3. This result suggests that the hydrogen-free TICS-SiO2 process effectively suppresses the hydrogen-induced reduction in the underlying oxide layer, which is regarded as the primary source of excess carrier in the oxide channel. By applying the TICS-SiO2 process, we successfully fabricated ESL-type IGZO TFTs with a field effect mobility over 10 cm2 V-1s-1 with improved reliability.
中文摘要 i
Abstract iii
Table of Contents v
List of Figures vii
List of Tables ix
Chapter 1. Introduction 1
1.1 General Background 1
1.1.1 Potential of TAOS as TFT Channel Material 2
1.1.2 Thin Film Transistor (TFT) 3
1.1.3 Mass Production Technology of Oxide TFT Backplane 4
1.1.4 SiO2 Deposition by PECVD 5
1.2 Motivation of This Work 6
1.3 Contents of This Thesis 6
Chapter 2. Characterization Methods 9
2.1 Characterization of SiO2 and IGZO Thin Films 9
2.1.1 X-Ray Refraction Diffraction Measurement 9
2.1.2 Hall Effect Measurement (Van-der-Pauw Measurement) 10
2.1.3 C-V Measurement 11
2.1.4 SIMS Measurement 14
2.2 TFT Characteristics 15
Chapter 3. Device Fabrication Processes 21
3.1 Thin Film Deposition Techniques 21
3.1.1 Magnetron Sputtering Deposition of Channel and Electrode……………………………………………………………22
3.1.2 Chemical Vapor Deposition of Thin-Film Dielectric 22
3.1.3 Dry Etching 24
3.2 Thin Film Transistor 25
3.3 TFT Device Fabrication Process 26
3.3.1 Gate Electrode Deposition 26
3.3.2 Gate Electrode Patterning 26
3.3.3 Gate Insulator Deposition 28
3.3.4 Channel Layer Deposition 28
3.3.5 Channel Layer Patterning 28
3.3.6 Channel Layer Annealing 29
3.3.7 Etch Stop Layer Deposition 29
3.3.8 Etch Stop Layer Patterning 29
3.3.9 Source/drain Electrode Deposition 30
3.3.10 Source/drain Electrode Patterning 30
3.3.11 Passivation Layer Deposition 30
3.3.12 Passivation Layer Annealing 30
3.3.13 Passivation Layer Patterning 31
3.3.14 SiO2 Deposition Using TICS Gas Source 31
Chapter 4. Experiment Results and Discussion 35
4.1 Comparison of TICS-SiO2 and SiH4-SiO2 Film Properties 35
4.2 Influence of SiO2 Deposition Process to Oxide Semiconductor 38
4.3 Characteristics of TFT Devices Fabricated by SiH4 and TICS Process 40
Chapter 5. Conclusion 49
5.1 Purpose of This Research 49
5.2 Conclusion of This Research 49
5.3 Future Work 50
References 51
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