跳到主要內容

臺灣博碩士論文加值系統

(44.212.99.208) 您好!臺灣時間:2024/04/17 18:18
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:陳彥廷
研究生(外文):CHEN, YAN-TING
論文名稱:超高速四階脈衝振幅調變電壓模態傳送機以及一個超低相位雜訊分數型次採樣鎖相迴路於四十奈米CMOS製程
論文名稱(外文):Ultra-High Speed PAM-4 Voltage-Mode Transmitters and an Ultra-Low Phase-Noise Fractional-N Sub-Sampling Phase-Locked Loop in 40nm CMOS process
指導教授:林鴻文林鴻文引用關係彭朋瑞
指導教授(外文):LIN, HUNG-WENPENG, PEN-JUI
口試委員:陳巍仁黃柏鈞郭岳芳王懷德彭朋瑞林鴻文
口試委員(外文):CHEN, WEI-ZENHUANG, PO-CHIUNKUO, YUE-FANGWANG, HUAI-DEPENG, PEN-JUILIN, HUNG-WEN
口試日期:2022-10-05
學位類別:博士
校院名稱:元智大學
系所名稱:電機工程學系甲組
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2022
畢業學年度:111
語文別:英文
論文頁數:130
中文關鍵詞:傳送器四階脈衝振幅調變前饋等化器電壓模態驅動器鎖相迴路分數型次採樣C類壓控震盪器相位內插器
外文關鍵詞:transmitterfour-level pulse amplitude modulationfeed-forward equalizervoltage-mode driverphase-locked loopfractional-Nsub-samplingClass-C VCOphase interpolator
相關次數:
  • 被引用被引用:0
  • 點閱點閱:349
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
本論文首先提出了一個112-Gb/s四階脈衝振幅調變電壓模態傳送機,電壓模態前饋等化器採用兩步粗調/細調技術,以減少前端電路的片數,同時保持足夠的分辨率。四分之一速率之多工器採用自動相位對齊技術來消除時序限制,從而移除所有重定時序之鎖存器,節省大量能源。此四階脈衝振幅調變傳送機在40-nm CMOS製程下設計和製造,在具有5.5-dB奈奎斯特損耗的板上芯片組件下展示112 Gb/的高質量眼圖,能源效率為3.89-pJ/b。
為了更進一步優化傳送機的效能,本論文針對時脈產生器的部分提出了一個低功耗低相位雜訊之12~14.5-GHz分數倍次採樣鎖相迴路,藉由使用次採樣之結構,改善了帶內的相位雜訊,分數倍運作所需的多相位產生器由數字時間轉換器和相位內插器合力實現,以降低數字時間轉換器的總延遲,從而降低其抖動。在電壓控制震盪器的設計上,所設計的C類電壓控制震盪器在13.76 GHz時僅消耗3.2 mW,並在1-MHz偏移實現了-106-dBc/Hz的相位雜訊。採用 40-nm CMOS 技術設計和製造,在分數倍模式下運作時,能源消耗為10.2 mW,並且從1 kHz到100 MHz的方均根抖動積分為 111 fs,達到249 dB的品質因數 (FoM)。
本論文提出的第二個傳送機架構致力於設計一個省電的四階脈衝振幅調變傳送機,其中採用了前述的次採樣鎖相迴路,並將最高速的2:1多工器合併到驅動器中,以減少全速率的節點達到省電之目的,為了進一步降低功耗,使用資料轉態點取樣之技術,將時脈速率降低為四分之一以節省時脈分佈之功耗,此外,本論文提出了一種用於實現電壓模態前饋等化器的新配置,該方法可以顯著降低電壓模式前饋等化器的佈局複雜度,提高輸出帶寬。此四階脈衝振幅調變傳送機在40-nm CMOS製程下設計和製造,在具有5-dB奈奎斯特損耗的板上芯片組件下展示100Gb/的高質量眼圖,能源效率2.39-pJ/b。
This thesis proposes a 112-Gb/s PAM-4 voltage-mode transmitter (TX) architecture. In the first TX, a two-step coarse- /fine-tuning technique is adopted in the voltage-mode FFE to reduce the number of front-end slices while maintaining the same resolution. The quarter-rate 4:1 MUX incorporates an automatic phase alignment technique to eliminate the timing constraint. As a result, all of the retiming latches can be removed, saving significant power. Designed and fabricated in 40-nm CMOS, the PAM-4 TX demonstrates a high-quality eye diagram at 112 Gb/s with 3.89-pJ/b energy efficiency under a chip-on-board assembly with 5.5-dB Nyquist loss.
In order to further optimize the transmitter’s performance, this thesis proposes a 12~14.5-GHz low-power low-phase-noise fractional-N sub-sampling phase-locked loop (SSPLL) for the clock generator of the transmitter. Using the sub-sampling topology, the in-band phase noise can be improved significantly. The multi-phase generation required for the fractional-N operation is implemented by both the digital-to-time-converter (DTC) and the phase interpolator (PI) to reduce the total delay required by the DTC, thereby suppressing the DTC intrinsic jitter. In the VCO design, the class-C VCO consumes only 3.2 mW at 13.76 GHz while achieving106-dBc/Hz phase noise at 1-MHz offset. Designed and fabricated in 40-nm CMOS technology, the PLL operating in fractional-N mode consumes 10.2 mW of power. The RMS jitter integrated from 1 kHz to 100 MHz is 111 fs, arriving at a figure of merit (FoM) of 249 dB.
The second PAM-4 voltage-mode transmitter architecture proposed in this thesis is focus on designing a power-efficient PAM-4 TX, which incorporates the SSPLL and merges the highest speed 2:1 multiplexer into the source-series terminated (SST) driver to reduce the full-rate nets to save power. In order to further reduce power consumption, the data-transition-sampling technology is used to reduce the clock rate to half to save the power consumption of clock distribution. In addition, a new configuration for implementing voltage-mode FFE is proposed to avoid the driver being segmented. The method can significantly decrease the layout complexity of a voltage-mode FFE, improving the output bandwidth. Designed and fabricated in 40-nm CMOS, the PAM-4 TX achieves a maximum data rate of 100 Gb/s with 2.39-pJ/b energy efficiency under a chip-on-board assembly with 5-dB Nyquist loss.
論文口試委員審定書 iii
摘 要 iv
誌 謝 viii
CONTENTS x
LIST OF FIGURES xiii
LIST OF TABLES xix
Chapter 1 Introduction 2
1.1 Motivation 2
1.2 Recent Research 5
1.2.1 TX 5
1.2.2 PLL 11
1.3 Organization of the Thesis 14
Chapter 2 Theorem of TXs and PLLs 15
2.1 Four-Level Pulse Amplitude Modulation 15
2.1.1 level separation mismatch ratio (RLM) 16
2.1.2 Transmitter signal-to-noise-and-distortion ratio (SNDR) 19
2.2 Multiplexer (MUX) 22
2.2.1 Full-Rate MUX 22
2.2.2 Half-Rate MUX 23
2.2.3 Quarter-Rate MUX 27
2.3 Driver 29
2.3.1 Voltage-Mode Logic Driver (VML) 29
2.3.2 Current-Mode Logic Driver (CML) 30
2.4 Phase-Locked Loops 31
2.4.1 Phase and Frequency Detector (PFD) 33
2.4.2 Charge Pump (CP) 34
2.4.3 Loop Filter 36
2.4.4 Voltage-Controlled Oscillator(VCO) 38
Chapter 3 A 112-Gb/s PAM-4 Voltage-Mode Transmitter with Four-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40-nm CMOS 42
3.1 Concept of Two-Step FFE in the Voltage-Mode TX 42
3.2 TX Architecture 45
3.3 Building Blocks 47
3.3.1 Two-Step FFE Driver 47
3.3.2 CMOS 4:1 MUX With Automatic Phase Alignment 52
3.3.3 Predriver 53
3.3.4 Duty-Cycle/Quadrature-Phase Calibration 55
3.4 Experimental Results 57
Chapter 4 A 12−14.5-GHz 10.2-mW −249-dB FoM Fractional-N Subsampling PLL with a High-Linearity Phase Interpolator in 40-nm CMOS 61
4.1 Operation of Fractional-N SSPLLs 61
4.2 High-Linearity Phase-Interpolator 63
4.3 Fractional-N SSPLL Architecture 71
4.4 Building Blocks 72
4.4.1 Delay Calculator 72
4.4.2 Sub-Sampling PD/CP & Pulser 73
4.4.3 PFD with Dead Zone 75
4.4.4 Class-C VCO 76
4.5 Phase Noise Analysis 78
4.6 Experimental Results 80
Chapter 5 A low-power 100-Gb/s PAM-4 Volt-age-Mode Transmitter with High-Resolution Unsegmented Three-Tap FFE in 40-nm CMOS 86
5.1 High-Resolution Unsegmented Voltage-Mode FFE 86
5.2 TX Architecture 90
5.3 Building Blocks 92
5.3.1 2:1 MUX Driver 92
5.3.2 Low Power 64:4 MUX 93
5.3.3 ILRO with Fine QEC 94
5.3.4 Duty-Cycle/Quadrature-Phase Calibration 97
5.4 Experimental Results 101
Chapter 6 Conclusions 104
REFERENCE 106

[1]J. Kim , A. Balankutty, R. K. Dokania, A. Elshazly, H. S. Kim, S. Kundu, D. Shi, S. Weaver, K. Yu, and F. O’Mahony, “A 112 Gb/s PAM-4 56 Gb/s NRZ reconfigurable transmitter with three-tap FFE in 10-nm FinFET,” IEEE Journal of Solid-State Circuits, vol. 54, no. 1, pp. 29–42, Jan. 2019.
[2]Z. Toprak-Deniz, J. E. Proesel, J. F. Bulzacchelli, H. A. Ainspan, T. O. Dickson, M. P. Beakes, and M. Meghelli, “A 128-Gb/s 1.3-pJ/b PAM-4 transmitter with reconfigurable 3-Tap FFE in 14-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 55, no. 1, pp. 19–26, Jan. 2020.
[3]Y. Krupnik, Y. Perelman, I. Levin, Y. Sanhedrai, R. Eitan, A. Khairi, Y. Shifman, Y. Landau, U. Virobnik, N. Dolev, A. Meisler, and A. Cohen, “112-Gb/s PAM4 ADC-based SERDES receiver with resonant AFE for long-reach channels,” IEEE Journal of Solid-State Circuits, vol. 55, no. 4, pp. 1077–1085, Apr. 2020.
[4] E. Groen, C. Boecker, M. Hossain, R. Vu, S. Vamvakos, H. Lin, S. Li, M. van Ierssel, P. Choudhary, N. Wang, M. Shibata, M. H. Taghavi, N. Nguyen, S. Desai, “6.3 a 10-to-112Gb/s DSP-DAC-Based transmitter with 1.2 Vppd output swing in 7nm FinFET,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2020, pp. 120–121.
[5]X. Zheng, H. Ding, F. Zhao, D. Wu, L. Zhou, J. Wu, F. Lv, J. Wang, and X. Liu, “A 50–112-Gb/s PAM-4 transmitter with a fractionalspaced FFE in 65-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 55, no. 7, pp. 1864–1876, Jul. 2020.
[6]T. Ali et al., “6.2 a 460 mW 112Gb/s DSP-based transceiver with 38dB loss compensation for next-generation data centers in 7nm FinFET technology,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2020, pp. 118–119.
[7]C. Menolfi, M. Braendli, P. A. Francese, T. Morf, A. Cevrero, M. Kossel, L. Kull, D. Luu, I. Ozkaya, T. Toifl, “A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2018, pp. 104–105.
[8]K. Tan et al., “A 112-Gb/s PAM4 transmitter in 16nm FinFET,” in Proc. IEEE Symp. VLSI Circuits, Jun. 2018, pp. 45–46.
[9]Common Electrical I/O (CEI)-112G, Optical Interconnect Forum (OIF). Accessed: Jul. 2, 2020. [Online]. Available:https://www.oiforum.com/technical-work/hot-topics/common-electrical-interface-cei-112g-2/
[10]K. L. Chan, K. H. Tan, Y. Frans, J. Im, P. Upadhyaya, S. W. Lim, A. Roldan, N. Narang, C. Y. Koay, H. Zhao, P.-C. Chiang, and K. Chang, “A 32.75-Gb/s voltage-mode transmitter with threetap FFE in 16-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 52, no. 10, pp. 2663–2678, Oct. 2017.
[11]M. A. Kossel, V. Khatri, M. Braendli, P. A. Francese, T. Morf, S. A. Yonar, M. Prathapan, E. J. Lukes, R. A. Richetta, C. Cox, “An 8b DAC-based SST TX using metal gate resistors with 1.4pJ/b efficiency at 112Gb/s PAM4 and 8-taps FFE in 7nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2021, pp. 130–131.
[12]X. Gao, E. Klumperink, B. Nauta, “Sub-sampling PLL techniques,” IEEE CICC, pp. 1-8, Sep. 2015.
[13]Z. Zhang, G. Zhu, C. P. Yue, “A 0.65V 12-to-16GHz sub-sampling PLL with 56.4fsrms integrated jitter and -256.4dB FoM, ” IEEE Journal of Solid-State Circuits, vol. 55, pp. 1665 – 1683, Jun. 2020.
[14]T. Siriburanon, S. Kondo, M. Katsuragi, H. Liu, K. Kimura, W. Deng, K. Okada, A. Matsuzawa, “A low-power low-noise mm-wave subsampling PLL using dual-step-mixing ILFD and tail-coupling quadrature injection-locked oscillator for IEEE 802.11ad,” IEEE Journal of Solid-State Circuits, vol. 51, pp. 1246 – 1260, Mar. 2016.
[15]K. Raczkowski, N. Markulic, B. Hershberg, J. Craninckx, “A 9.2–12.7 GHz wideband fractional-N subsampling PLL in 28 nm CMOS with 280 fs RMS jitter,” IEEE Journal of Solid-State Circuits, vol. 50, pp. 1203 – 1216, Mar. 2015.
[16]W. Wu, C.-W. Yao, C. Guo, P.-Y. Chiang, P.-K. Lau, L. Chen, S.-W. Son, T.- B. Cho, “A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2021, pp. 444–446.
[17]W. Wu, C.-W. Yao, K. Godbole, R. Ni, P.-Y. Chiang, Y. Han, Y. Zuo, A. Verma, I. S.-C. Lu, S. W. Son, and T. B. Cho, “A 28-nm 75-fsrms Analog Fractional-N Sampling PLL with a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2020, pp. 274–276.
[18]P.-J. Peng, Y.-T. Chen, S.-T. Lai, and H.-E. Huang, “A 112-Gb/s PAM-4 Voltage-Mode Transmitter With Four-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 56, no. 7, pp. 2123–2131, Jul. 2021.
[19]Y.-T. Chen, P.-J. Peng, H.-W. Lin, "A 12–14.5-GHz 10.2-mW −249-dB FoM Fractional-N Subsampling PLL With a High-Linearity Phase Interpolator in 40-nm CMOS," IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, vol. 30, no. 5, pp. 634-643, Mar. 2022.
[20]Y.-T. Chen, P.-J. Peng, H.-W. Lin, "A 100-Gb/s PAM-4 Voltage-Mode Transmitter With High-Resolution Unsegmented Three-Tap FFE in 40-nm CMOS," IEEE Solid-State Circuit Letters, vol. 5, pp. 218-221, Aug. 2022.
[21]IEEE Standard for Ethernet, IEEE Standard 802.3-2018, 2018.
[22]F. M. Gardner, Phaselock Techniques, Second Edition, New York: Wiley & Sons, 1979.
[23]B. Razavi, RF Microelectronics., Second Edition, Prentice-Hall, 2012.
[24]E. Depaoli, H. Zhang, M. Mazzini, W. Audoglio, A. Andrea Rossi, G. Albasini, M. Pozzoni, S. Erba, E. Temporiti, and A. Mazzanti, “A 64 Gb/s low-power transceiver for short-reach PAM-4 electrical links in 28-nm FDSOI CMOS,” IEEE Journal of Solid-State Circuits, vol. 54, no. 1, pp. 6–17, Jan. 2019..
[25]J. Kim, A. Balankutty, A. Elshazly, Y.-Y. Huang, H. Song, K. Yu, F. O’Mahony, “3.5 a 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2015, pp. 60–61.
[26]P.-J. Peng, Y.-T. Chen, S.-T. Lai, C.-H. Chen, H.-E. Huang, and T. Shih, “6.7 a 112Gb/s PAM-4 voltage-mode transmitter with 4-tap two-step FFE and automatic phase alignment techniques in 40nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2019, pp. 124–126.
[27]T. Shibasaki et al., “3.5 a 56Gb/s NRZ-electrical 247 mW/lane seriallink transceiver in 28nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Jan. 2016, pp. 64–65.
[28]P.-J. Peng, Y.-T. Chen, S.-T. Lai, C.-H. Chen, H.-E. Huang, H-H Lu, and T-C Yu, “A 50-Gb/s quarter-rate voltage-mode transmitter with three-tap FFE in 40-nm CMOS,” in Proc. IEEE 44th Eur. Solid State Circuits Conf. (ESSCIRC), Sep. 2018, pp. 174–177.
[29]A. A. Hafez, M.-S. Chen, and C.-K.-K. Yang, “A 32–48 Gb/s serializing transmitter using multiphase serialization in 65 nm CMOS technology,” IEEE Journal of Solid-State Circuits, vol. 50, no. 3, pp. 763–775, Mar. 2015.
[30]Y. Frans, S. McLeod, H. Hedayati, M. Elzeftawi, J. Namkoong, W. Lin, J. Im, P. Upadhyaya, and K. Chang, “A 40-to-64 Gb/s NRZ transmitter with supply-regulated front-end in 16 nm FinFET,” IEEE Journal of Solid-State Circuits, vol. 51, no. 12, pp. 3167–3177, Dec. 2016.
[31]A. T. Narayanan, M. Katsuragi, K. Kimura, S. Kondo, K. K. Tokgoz, K. Nakata, W. Deng, K. Okada, and A. Matsuzawa, "A fractional-N sub-sampling PLL using a pipelined phase-interpolator with an FoM of -250 dB," IEEE Journal of Solid-State Circuits, vol. 51, pp. 1630 – 1640, July 2016.
[32]D. Liao, F. F. Dai, B. Nauta, and E. A. M. Klumperink, "A 2.4-GHz 16-phase sub-sampling fractional-N PLL with robust soft loop switching," IEEE Journal of Solid-State Circuits, vol. 53, pp. 715 – 727, Mar 2018.
[33]A. Jakobsson, A. Serban, and S. Gong, “A low-noise RC-based phase interpolator in 16-nm CMOS,” IEEE Trans. Circuits Syst. II, vol. 66, no. 1, pp. 1-5, Jan. 2019.
[34]X. Gao, E. A. M. Klumperink, G. Socci, M. Bohsali, and B. Nauta, “Spur reduction techniques for phase-locked loops exploiting a sub-sampling phase detector,” IEEE Journal of Solid-State Circuits, vol. 45, pp. 1809 – 1821, Aug. 2010.
[35]J. Tao, C.-H. Heng, “A 2.2-GHz 3.2-mW DTC-free sampling ΔΣ fractional-N PLL with −110-dBc/Hz in-band phase noise and −246-dB FoM and −83-dBc reference spur,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 66, pp. 3314–3329, Sep. 2019.
[36]M. Mercandelli, A. Santiccioli, A. Parisi, L. Bertulessi, D. Cherniak, A. L. Lacaita, C. Samori, S. Levantino, “A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 274-275, Feb. 2020.
[37]W. E. Halwagy, A. Nag, P. Hisayasu, F. Aryanfar, P. Mousavi, and M. Hossain, “A 28-GHz quadrature fractional-N frequency synthesizer for 5G transceivers with less than 100-fs jitter based on cascaded PLL architecture,” IEEE Trans. Microw. Theory Techn., vol. 65, no. 2, pp. 396–413, Feb. 2017.
[38]V. Szortyka, Q. Shi, K. Raczkowski , B. Parvais , M. Kuijk , P. Wambacq, "A 42 mW 230 fs-jitter sub-sampling 60 GHz PLL in 40 nm CMOS," IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 366-368, Feb. 2014.
[39]A. Mazzanti, P. Andreani, “Class-C harmonic CMOS VCOs, with a general result on phase noise,” IEEE Journal of Solid-State Circuits, vol. 43, pp. 2716 – 2729, Dec. 2008.
[40]D. Turker, A. Bekele, P. Upadhyaya, B. Verbruggen, Y. Cao, S. Ma, C. Erdmann, B. Farley, Y. Frans, K. Chang, “A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 378-379, Feb. 2018.
[41]Y. Chang, A. Manian, L. Kong, and B. Razavi, " An 80-Gb/s 44-mW Wireline PAM4 Transmitter," IEEE Journal of Solid-State Circuits, vol. 53, pp. 2214-2226, Aug. 2018.
[42]P.-J. Peng, S.-T. Lai, W.-H. Wang, C.-W. Lin, W.-C. Huang, T. Shih, “A 100Gb/s NRZ Transmitter with 8-Tap FFE Using a 7b DAC in 40nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2020, pp. 130–131.
[43]S. Chen, L. Zhou, I. Zhuang, J. Im, D. Melek, J. Namkoong, M. Raj, J. Shin, Y. Frans, K. Chang, “A 4-to-16GHz Inverter-Based Injection-Locked Quadrature Clock Generator with Phase Interpolators for Multi-Standard I/Os in 7nm FinFET,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2018, pp. 390–392.
[44]Z. Wang, Y. Zhang, Y. Onizuka, P. R. Kinget, “A High-Accuracy Multi-Phase Injection-Locked 8-Phase 7GHz Clock Generator in 65nm with 7b Phase Interpolators for High-Speed Data Links,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2021, pp. 186–187.

電子全文 電子全文(網際網路公開日期:20271020)
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關期刊