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研究生:薛詠方
研究生(外文):Yung Fang Hsueh
論文名稱:六氟化硫電漿處理之二硫化鉬於背閘極電晶體特性研究
論文名稱(外文):Investigation of the Electrical Characteristics of Back-Gate MoS2 Transistors Treated with SF6 Plasma
指導教授:賴朝松
指導教授(外文):C. S. Lai
口試委員:李耀仁楊家銘賴朝松
口試委員(外文):Y. J. LeeC. M. YangC. S. Lai
口試日期:2024-07-16
學位類別:碩士
校院名稱:長庚大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2024
畢業學年度:112
語文別:中文
論文頁數:98
中文關鍵詞:二維材料二硫化鉬電晶體電漿摻雜閘極氧化層
外文關鍵詞:Two-dimensional materialsMolybdenum disulfide (MoS2)TransistorsPlasma dopingGate oxide layer
相關次數:
  • 被引用被引用:0
  • 點閱點閱:5
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  • 下載下載:1
  • 收藏至我的研究室書目清單書目收藏:0
二硫化鉬(Molybdenum Disulfide, MoS2),屬於過渡金屬硫族化物,已成為近年來熱門的研究主題。它的單層厚度僅為0.65納米,由S-Mo-S結構形成的六方晶格層狀結構具有卓越的物理和化學特性。單層二硫化鉬展示了1.8 eV的直接能隙,使得基於此材料的電晶體具有極高的on/off比和良好的載子遷移率。
然而,二硫化鉬電晶體的發展仍面臨挑戰,特別是在金屬與二硫化鉬的界面處存在高電阻問題,這主要由硫空位缺陷和費米能階被釘住(Fermi Level Pinning)所導致,這種現象會阻礙載子的流動,影響電晶體的性能。
本研究的目的是實現將二硫化鉬(MoS2)薄膜從n型轉換為p型,以提升其在先進電子元件中的應用潛力。為達成此目的,我們將使用高密度電漿系統(Inductively-Coupled-Plasma, ICP)摻雜技術,通過引入適當的摻雜劑來實現二硫化鉬的p型摻雜,對二硫化鉬薄膜進行表面處理,研究在不同電漿處理條件下電晶體摻雜的效果及其電性特性,且探討電漿處理對硫空位缺陷的修復以及費米能階釘住現象的影響。透過此研究,期望能夠有效地降低金屬-二硫化鉬界面的高電阻問題,進而提升二硫化鉬電晶體的on/off比和載子遷移率,使其在p型模式下也能展現出優異的電子性能,推動二維材料在先進電子元件領域中的應用。
Molybdenum disulfide (MoS2), a transition metal dichalcogenide, has emerged as a significant research focus recently. Its monolayer thickness is merely 0.65 nanometers, composed of an S-Mo-S hexagonal lattice structure, which confers exceptional physical and chemical properties. The monolayer MoS2 exhibits a direct bandgap of 1.8 eV, leading to transistors with extremely high on/off ratios and robust carrier mobility.
Nevertheless, MoS2 transistors face developmental challenges, particularly high resistance at the interface between metal and MoS2, mainly caused by sulfur vacancy defects and Fermi level pinning, which impedes carrier movement and degrades transistor performance.
The aim of this study is to achieve the conversion of MoS2 thin films from n-type to p-type to enhance their application potential in advanced electronic devices. To achieve this, we will use high-density plasma systems (Inductively-Coupled Plasma, ICP) and doping techniques by introducing appropriate dopants to realize p-type doping of MoS2. We will conduct surface treatments on MoS2 films and study the doping effects and electrical properties of transistors under different plasma treatment conditions. Furthermore, we will investigate the effects of plasma treatment on the repair of sulfur vacancy defects and the mitigation of Fermi level pinning. Through this research, we aim to effectively reduce the high resistance at the metal- MoS2 interface, thereby improving the on/off ratio and carrier mobility of MoS2 transistors. This will enable them to exhibit excellent electronic performance in p-type mode and promote the application of two-dimensional materials in advanced electronic devices.
摘要 i
Abstract ii
目錄 iv
圖目錄 vii
表目錄 xi
第一章 簡介 - 1 -
1.1 背景 - 1 -
1.2 過渡金屬二硫化物 - 2 -
1.2.1 二維材料電晶體 - 2 -
1.2.2 二維材料的結構特性及其應用 - 3 -
1.2.3 MoS2結構與特性 - 3 -
1.2.4 二硫化鉬製備方法 - 4 -
1.3 場效應晶體管(Field-Effect Transistor,FET) - 5 -
1.4 二硫化鉬電晶體性能與機制研究 - 5 -
1.4.1 電荷載子動力學與介面電阻特性 - 5 -
1.4.2閘極調控下的二硫化鉬通道電流分析 - 6 -
1.4.3 界面機制對MoS2電晶體特性的影響 - 6 -
1.4.4 單層二硫化鉬特性 - 7 -
1.5 電漿原理及基本反應 - 8 -
1.5.1 六氟化硫(SF6)特性 - 9 -
1.5.2 SF6二硫化鉬電漿摻雜的氟化反應機制 - 9 -
1.5.3 氟摻雜後的二硫化鉬電性變化 - 10 -
1.6 研究動機 - 11 -
第二章 研究方法及實驗架構 - 19 -
2.1 實驗設備介紹 - 19 -
2.1.1 高密度電漿系統(Inductively-Coupled-Plasma, ICP) - 19 -
2.1.2 電子槍蒸鍍系統(E-Gun Evaporation, E-Gun) - 20 -
2.1.3 黃光微影(Lithography) - 20 -
2.1.4熱阻式蒸鍍機(Thermal Evaporator) - 21 -
2.1.5反應離子蝕刻(Reactive Ion Etching, RIE) - 21 -
第三章 二硫化鉬電晶體之製程與電漿處理技術研究 - 27 -
3.1 簡介 - 27 -
3.2元件製備 - 27 -
3.2.1 MoS2生長 - 27 -
3.2.2 MoS2轉印 - 28 -
3.2.3 SF6電漿摻雜蝕刻 - 28 -
3.2.4 黃光微影(電極定義) - 29 -
3.2.5 E-gun沉積電極和Lift off製程 - 29 -
3.2.6 黃光微影(通道定義) - 29 -
3.2.7 ICP-RIE(CF4)定義通道 - 30 -
第四章 背閘極式二硫化鉬電晶體基本電性量測 - 34 -
4.1 簡介 - 34 -
4.2 量測方法介紹 - 34 -
4.3 拉曼光譜材料分析(Raman) - 34 -
4.3.1 拉曼光譜分析 - 36 -
4.4 X射線光電子能譜(XPS) - 37 -
4.4.1 表面元素分析 - 38 -
4.4.2 XPS元素分析以及結果與討論 - 39 -
4.5 結果與討論 - 41 -
4.5.1 背閘極式二硫化鉬電晶體的載子遷移率 - 41 -
4.5.2 ID-VD電性量測及分析 - 42 -
4.5.3 ID-VG電性量測及分析 - 43 -
4.5.4 背閘極式二硫化鉬電晶體的Ion 提升百分比 - 44 -
4.6 本章總結 - 45 -
第五章 結論與未來展望 - 76 -
5.1結論 - 76 -
5.2 未來展望 - 77 -
參考文獻 - 78 -

圖目錄
圖1-1石墨烯的結構示意圖其不同形式,有富勒希球,奈米碳管與層層堆疊的石墨烯 - 13 -
圖1-2二維材料分類表 - 13 -
圖1-3 單層二硫化鉬電晶體特性 - 14 -
圖1-4 二硫化鉬的三維結構圖 - 14 -
圖1-5 塊狀及單層二硫化鉬能帶示意圖 - 15 -
圖1-6 利用硫化Mo金屬薄膜來得到單層或多層的MoS2製程示意圖 - 15 -
圖1-7 物理與化學蝕刻機制 - 16 -
圖1-8 電漿蝕刻步驟示意圖 - 17 -
圖1-9 (a) SF6電漿處理對多層二硫化鉬(MoS2)的摻雜過程示意圖(b) 未經處理的N型MoS2以及經SF6處理後的P型MoS2 - 17 -
圖1-10 p型摻雜MoS2與n型MoS2間的能帶結構變化示意圖- 18 -
圖2-1感應耦合電漿 - 23 -
圖2-2 ICP蝕刻原理示意圖 - 23 -
圖2-3 Filter過濾器示意圖 - 24 -
圖2-4 熱阻式蒸鍍機 - 25 –
圖2-5 Thermal生長原理示意圖 - 25 -
圖2-6 反應離子蝕刻 - 26 –
圖2-7 RIE蝕刻原理示意圖 - 26 -
圖3-1二硫化鉬轉印技術示意圖 - 31 -
圖3-2 製程流程示意圖 - 32 -
圖3-3 元件示意圖 - 33 -
圖4-1 量測方式示意圖 - 47 -
圖4-2二硫化鉬分子兩種震動模式E12g模式和A1g模式 - 47 -
圖4-3不同層數的二硫化鉬拉曼光譜峰值示意圖 - 48 -
圖4-4二硫化鉬pristine拉曼光譜 - 48 -
圖4-5拉曼頻率隨功率變化及其誤差值 - 49 -
圖4-6 MoS2在不同電漿瓦數轟擊後的拉曼光譜圖譜 - 50 -
圖4-7 (a)至(e) SF6處理後各元素(S, Mo, F, O, C) 光電子能譜分析
- 55 -
圖4-8 L=3um未經電漿處理與經電漿處理的開關比比較 - 56 -
圖4-9不同功率下MoS2電晶體L=3um的開關比變化 - 56 -
圖4-10 L=5um未經電漿處理與經電漿處理的開關比比較 - 57 -
圖4-11不同功率下MoS2電晶體L=5um的開關比變化 - 57 -
圖4-12 L=10um未經電漿處理與經電漿處理的開關比比較 - 58 -
圖4-13不同功率下MoS2電晶體L=10um的開關比變化 - 58 -
圖4-14未經電漿處理控制片L=3um MoS2 I_D-V_D特性圖 - 59 -
圖4-15 SF6摻雜10W電漿處理L=3um MoS2 I_D-V_D特性圖 - 59 -
圖4-16 SF6摻雜50W電漿處理L=3um MoS2 I_D-V_D特性圖 - 60 -
圖4-17 SF6摻雜100W電漿處理L=3um MoS2 I_D-V_D特性圖- 60 -
圖4-18 SF6摻雜125W電漿處理L=3um MoS2 I_D-V_D特性圖- 61 -
圖4-19 SF6摻雜250W電漿處理L=3um MoS2 I_D-V_D特性圖 -61 -
圖4-20 SF6摻雜500W電漿處理L=3um MoS2 I_D-V_D特性圖 -62 -
圖4-21未經電漿處理控制片L=5um MoS2 I_D-V_D特性圖 - 63 -
圖4-22 SF6摻雜10W電漿處理L=5um MoS2 I_D-V_D特性圖 - 63 -
圖4-23 SF6摻雜50W電漿處理L=5um MoS2 I_D-V_D特性圖 - 64 -
圖4-24 SF6摻雜100W電漿處理L=5um MoS2 I_D-V_D特性圖- 64 -
圖4-25 SF6摻雜125W電漿處理L=5um MoS2 I_D-V_D特性圖- 65 -
圖4-26 SF6摻雜250W電漿處理L=5um MoS2 I_D-V_D特性圖- 65 -
圖4-27 SF6摻雜500W電漿處理L=5um MoS2 I_D-V_D特性圖- 66 -
圖4-28未經電漿處理控制片L=10um MoS2 I_D-V_D特性圖 - 67 -
圖4-29 SF6摻雜10W電漿處理L=10um MoS2 I_D-V_D特性圖- 67 -
圖4-30 SF6摻雜50W電漿處理L=10um MoS2 I_D-V_D特性圖- 68 -
圖4-31 SF6摻雜100W電漿處理L=10um MoS2 I_D-V_D特性圖- 68 -
圖4-32 SF6摻雜125W電漿處理L=10um MoS2 I_D-V_D特性圖- 69 -
圖4-33 SF6摻雜250W電漿處理L=10um MoS2 I_D-V_D特性圖- 69 -
圖4-34 SF6摻雜500W電漿處理L=10um MoS2 I_D-V_D特性圖- 70 -
圖4-35不同電漿瓦數、相同電壓VG=-5V摻雜於L=3um MoS2 I_D-V_D特性圖 - 71 -
圖4-36 不同電漿瓦數、相同電壓VG=0V摻雜於L=3um MoS2 I_D-V_D特性圖 - 71 -
圖4-37 不同電漿瓦數、相同電壓VG=5V摻雜於L=3um MoS2 I_D-V_D特性圖 - 72 -
圖4-38不同電漿瓦數摻雜L=3um MoS2 I_D-V_G特性圖 - 73 -
圖4-39不同電漿瓦數摻雜L=5um MoS2 I_D-V_G特性圖 - 73 -
圖4-40不同電漿瓦數摻雜L=10um MoS2 I_D-V_G特性圖 - 74 -

表目錄
表1-1二維材料各個材料特性比較表 - 16 -
表3-1利用高密度電漿系統在300nm的P型重摻雜SiO2基板表面上SF6電漿處理之實驗參數 - 33 -
表4-1不同電漿處理功率之間的on current提升百分比 - 75 -
表4-2各個電漿處理功率相對於10W之間的on current提升百分比 - 75 -
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