臺灣博碩士論文加值系統

唯讀記憶體具有非揮發性、高可靠度、低面積、高製程整合性等特性已廣泛應用於系統晶片中以儲存大量資料或指令編碼使用。唯讀記憶體主要分為NAND-type唯讀記憶體（NAND-type ROM）和 NOR-type 唯讀記憶體（NOR-type ROM）。
本論文的研究為NAND-type唯讀記憶體和低電壓高速感測放大器，為了設計NAND-type唯讀記憶體於低電壓下能夠正常操作，並且具有低漏電流之特性，本論文對於 NAND型唯讀記憶體進行設計。其中，唯讀記憶體的工作電壓為0.5V，電晶體操作在次臨界區，而低電壓感測放大器設計，將面臨到PVT變異影響，本論文提出的感測放大器，為栓鎖型感測放大器，利用參考記憶體單元和一般的記憶體單元之間的電壓差來做比較，達到電路操作於次臨界區下，具有高速且抗PVT變異的能力。最終以CIC018製程且工作電壓為0.5V下成功實現一128kb×8容量大小的NAND型唯讀記憶體，並且經過模擬驗證，在工作頻率1.25MHz下，可以讓唯讀記憶體正常讀取資料。

The non-volatile nature, high reliability, small footprint, and high process integration of read-only memory (ROM) have made it widely used in system-on-chip designs for storing large amounts of data or instruction codes. ROM is primarily categorized into NAND-type ROM and NOR-type ROM. This paper focuses on NAND-type ROM and low-voltage high-speed sense amplifiers. The research aims to design NAND-type ROM that operates effectively at low voltages with low leakage current characteristics.
This paper focuses on the design of NAND-type read-only memory (ROM) and a low-voltage high-speed sense amplifier. The primary objective is to enable NAND-type ROM to operate effectively at low voltages while maintaining low leakage current characteristics. The ROM operates at a voltage of 0.5V, with transistors functioning in the subthreshold region.The design of the low-voltage sense amplifier is critical due to its susceptibility to Process, Voltage, and Temperature (PVT) variations. The paper proposes a latch-type sense amplifier that compares voltage differentials between reference memory cells and standard memory cells. This approach allows the circuit to operate effectively in the subthreshold region, achieving high speed and resilience against PVT variations. Using the CIC018 process and operating at 0.5V, the paper successfully implements a NAND-type ROM with a capacity of 128kb×8. Simulation results validate that the ROM can reliably read data at a frequency of 1.25MHz.

目 錄
中文摘要 i
Abstract ii
目錄 iv
圖目錄 vii
表目錄 xi
第一章 序論 1
1.1 研究背景 2
1.2 研究動機 3
1.3 章節介紹 3
第二章 NAND-Type唯讀記憶體周邊電路 4
2.1 ROM Cell Array介紹 5
2.2固定VREF的感測電路 7
2.3 Data-Aware Sensing Reference Scheme (DASR) 9
2.4 Dynamic Split Source-Line Scheme (DSSL) 11
2.5 Sensing Latch 13
2.6 A conventional voltage-mode sense amplifier 14
2.7 Low power sense amplifier 16
第三章 低電壓NAND type ROM架構 19
3.1電路架構 19
3.1.1 電路運作說明 19
3.1.2 1Mb (128kb×8) NAND type ROM Array架構 20
A. NAND type Cell架構和操作 23
3.2 周邊電路架構與操作說明 24
3.2.1 輸入緩衝器 25
3.2.2列解碼器 26
3.2.3行解碼器和行選擇器 29
3.2.4 字元線和字串閘驅動器(WL and SG Driver) 31
3.3 感測放大器電路架構與操作說明 32
3.3.1 高速栓鎖型感測放大器(Latch-type Sense Amplifier) 33
A. 電路設計理念 34
B. 電路操作原理 38
3.3.2 本論文感測放大器與其他感測放大器比較 41
第四章 模擬與比較 43
4.1 感測放大器模擬與比較 43
A. TT-corner 45
B. SS-corner 48
C. FF-corner 51
4.2 Pre-Layout Simulation和Post-Layout Simulation的結果比較 54
4.3不同的記憶單元排列方式與參考側記憶單元的位元線放電模擬結果 56
4.4 128kb×8 bits NAND type ROM的資料讀出模擬結果 58
第五章 總論與未來研究方向 62
5.1 總論 62
5.2 未來研究方向 63

參考文獻 64

圖目錄
圖2.1 NAND ROM Cell array 5
圖2.2 參考論文提出NAND ROM Cell array 6
圖2.3 固定參考電壓式感測電路 7
圖2.4 固定參考電壓式感測電路之位元線放電波形圖 8
圖2.5 Data-Aware Sensing Reference Scheme 9
圖2.6 DASR之位元線之放電波形圖 10
圖2.7 DSSL之時序圖 11
圖2.8 位元線電荷分享示意圖 12
圖2.9 Sensing Latch 13
圖2.10 (a) conventional voltage-mode sense amplifier (b) 時序圖 14
圖2.11 (a) Low power sense amplifier (b) 時序圖 16
圖3.1 NAND type ROM方塊圖 20
圖3.2 (a)1Mb NAND type ROM Array (b)各種不同的Cell排列方式 21-22
圖3.3 NAND type Cell (a)架構示意圖(b)佈局示意圖 24
圖3.4 輸入緩衝器電路 26
圖3.5 Dynamic Pseudo NMOS邏輯 28
圖3.6 7對128用於String Gate列解碼器電路 28
圖3.7 4對16用於字元線列解碼器電路 29
圖3.8 6對64行解碼器電路 29
圖3.9 64對1行選擇器電路 30
圖3.10 字元線驅動器電路 31
圖3.11字串閘驅動器電路 32
圖3.12 高速栓鎖型感測放大器和參考側記憶單元 34
圖3.13 (a)讀0的最差狀況、讀1的最差狀況
(b)位元線在各種讀取狀況的放電情形 37
圖3.14 (a)本論文提出之感測放大器與輸出緩衝器
(b)本論文提出之感測放大器操作時序圖 39-40
圖3.15 固定電壓感測電路 41
圖3.16 Data-Aware Sensing Reference Scheme(DASR) 42
圖4.1 在TT_25˚C_0.5V下，各種感測放大器讀0模擬結果 45
圖4.2 在TT_25˚C_0.5V下各種感測放大器讀1模擬結果 45
圖4.3 在TT_0˚C_0.5V下各種感測放大器讀0模擬結果 46
圖4.4 在TT_0˚C_0.5V下各種感測放大器讀1模擬結果 46
圖4.5 在TT_85˚C_0.5V下各種感測放大器讀0模擬結果 47
圖4.6 在TT_85˚C_0.5V下各種感測放大器讀1模擬結果 47
圖4.7 在SS_25˚C_0.5V下各種感測放大器讀0模擬結果 48
圖4.8 在SS_25˚C_0.5V下各種感測放大器讀1模擬結果 48
圖4.9 在SS_0˚C_0.5V下各種感測放大器讀0模擬結果 49
圖4.10 在SS_0˚C_0.5V下各種感測放大器讀1模擬結果 49
圖4.11 在SS_85˚C_0.5V下各種感測放大器讀0模擬結果 50
圖4.12 在SS_85˚C_0.5V下各種感測放大器讀1模擬結果 50
圖4.13 在FF_25˚C_0.5V下各種感測放大器讀0模擬結果 51
圖4.14 在FF_25˚C_0.5V下各種感測放大器讀1模擬結果 51
圖4.15 在FF_0˚C_0.5V下各種感測放大器讀0模擬結果 52
圖4.16 在FF_0˚C_0.5V下各種感測放大器讀1模擬結果 52
圖4.17 在FF_85˚C_0.5V下各種感測放大器讀0模擬結果 53
圖4.18 在FF_85˚C_0.5V下各種感測放大器讀1模擬結果 53
圖4.19感測放大器佈局圖 54
圖4.20 在TT_25˚C_0.5V下，本論文提出的感測放大器之Pre-Layout Simulation和Post-Layout Simulation讀0模擬結果比較 55
圖4.21 在TT_25˚C_0.5V下，本論文提出的感測放大器之Pre-Layout Simulation和Post-Layout Simulation讀1模擬結果比較 56
圖4.22 不同的讀0記憶單元排列方式的位元線放電模擬結果 57
圖4.23 不同的讀1記憶單元排列方式的位元線放電模擬結果 58
圖4.24 NAND type ROM讀01011000和01100111的模擬結果 60

表目錄
表4.1 本論文提出之唯讀記憶體的感測放大器比較 61

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