臺灣博碩士論文加值系統

隨著半導體技術的進步，電晶體尺寸微縮將面臨物理極限，也因此出現穿隧效應、短通道效應等問題，而單晶片三維整合技術將電晶體、記憶體單元等元件通過垂直堆疊的方式來突破極限，從而提高效能並節省空間。其中最大挑戰在於後段製程的溫度限制，涉及到金屬層的沉積、黃光製程及不同元件之間的連接，而氧化物半導體擁有低溫製程的優勢，同時具備寬能隙、高載子及高遷移率等優點，被視為未來應用極具發展性的材料。
本篇論文為非晶氧化物薄膜電晶體於後段製程之研究，通道層選用氧化銦並摻雜金屬鎢離子，藉此改善氧化銦氧空缺較多及穩定度不佳的問題，由於鎢離子擁有較高鍵結離能(720 kJ/mol)，因此能夠增強與氧之間的鍵結。近年來氧化物半導體以原子層沉積生長薄膜居多，而氧化銦鎢薄膜卻還是以化學氣相沉積為主，使用原子層沉積對於3D或複雜結構相當有利，此沉積方法的覆蓋率好、均勻度佳，同時可避免物理氣相沉積過程中的離子轟擊，降低製程時所造成的缺陷，因此本研究嘗試使用原子層沉積系統，沉積氧化銦鎢作為通道層，而此研究所使用的沉積手法也與傳統原子層沉積模式不同，一般原子層沉積方式為先後通入兩種前驅物，交錯循環下形成薄膜，本研究則選擇先單獨沉積氧化銦後，再沉積薄薄的鎢在上面做摻雜，展現有別以往的製程方式。
通道與介面缺陷也是造成穩定度不佳的來源之一，大部分會選擇退火來改善此處缺陷，本研究選擇氧化亞氮退火，而非常見的快速熱退火、氧退火等，由於氧化亞氮中氮與氧原子之間的鍵級小於氧氣的鍵級，因此更容易斷鍵出活性氧原子，並有效地擴散，改善介面或通道層中因氧缺陷造成的不穩定性。此外退火也有另一個作用，能夠提供熱能給鎢離子，使其能與氧化銦通道層完成摻雜，提升穩定性。
本實驗著重的兩項處理為鎢摻雜濃度及氧化亞氮退火調變，目的皆是在穩定度提升的情況下，仍保持相對優異的電性。經過最佳條件的摻雜與退火處理後，電性結果中的ID-VG轉移特性曲線及遷移率仍維持在相當高的水平，材料分析的X射線光電子能譜儀(XPS)結果也可看出，鎢-氧鍵結含量提升至24.62%與氧空缺減少至23.59%，穩定度測試中臨界電壓的偏移量約為0.01V。

With the advancement of semiconductor technology, transistor miniaturization faces physical limits, leading to issues such as tunneling effects and short-channel effects. To overcome these challenges, monolithic three-dimensional integration on a single chip vertically stacks transistors, memory units, and other components, thereby enhancing performance and saving space. The primary challenge lies in the temperature limitations of the backend process, which involves metal layer deposition, photolithography, and interconnections between different components. Oxide semiconductors are advantageous for low-temperature processing and possess properties such as a wide bandgap, high carrier concentration, and high mobility, making them promising materials for future applications.
This thesis investigates the use of amorphous oxide thin-film transistors in back-end-of-line (BEOL) processing. Indium oxide doped with tungsten ions was chosen for the channel layer to address the issues of high oxygen vacancy concentration and poor stability in indium oxide. Tungsten ions, with their high bond energy (720 kJ/mol), enhance the bonding with oxygen. While oxide semiconductors have predominantly been grown using atomic layer deposition (ALD) in recent years, indium-tungsten oxide films are still mainly deposited by chemical vapor deposition. ALD is beneficial for 3D or complex structures due to its excellent coverage, uniformity, and avoidance of ion bombardment during physical vapor deposition, thus reducing process-induced defects.
In this study, ALD was used to deposit indium-tungsten oxide as the channel layer. Unlike the traditional ALD method of alternating precursor cycles to form a film, this study first deposited indium oxide, followed by a thin tungsten layer for doping, showcasing a novel process.
Channel and interface defects are significant sources of instability. While annealing is commonly used to mitigate these defects, this study employed nitrous oxide (N2O) annealing instead of conventional rapid thermal annealing (RTA) or oxygen annealing. The bond energy between nitrogen and oxygen in N2O is lower than that of oxygen molecules, making it easier to generate active oxygen atoms and effectively diffuse them to improve the stability of the interface or channel layer caused by oxygen defects. Additionally, annealing provides thermal energy for tungsten ions to complete the doping process with the indium oxide channel layer, further enhancing stability.
The experiment focused on optimizing tungsten doping concentration and N2O annealing conditions to improve stability while maintaining excellent electrical properties. After doping and annealing under optimal conditions, the electrical characteristics, such as the ID-VG transfer curve and mobility, remained at high levels. X-ray photoelectron spectroscopy (XPS) analysis showed an increase in tungsten-oxygen bond content to 24.62% and a reduction in oxygen vacancies to 23.59%. Stability tests indicated a threshold voltage shift of approximately 0.01V.

摘要 i
Abstract ii
目次 iv
表目次 vi
圖目次 vii
第一章 緒論 1
1.1前言 1
1.2氧化物半導體 3
1.3薄膜沉積技術 5
1.3.1加熱型原子層沉積系統(Thermal ALD) 7
1.3.2電漿型原子層沉積系統(Plasma Enhanced ALD, PE-ALD) 8
1.4研究動機 9
1.5論文架構 10
第二章 鎢摻雜與退火處理及特徵參數介紹 11
2.1鎢摻雜與調變 11
2.2氧化亞氮退火處理 13
2.3薄膜電晶體之特徵參數 14
2.3.1臨界電壓(Threshold Voltage, VTH) 14
2.3.2次臨界擺幅(Sub-threshold Swing, SS) 15
2.3.3開關電流比(On/Off Current Ratio, ION/IOFF Ratio) 15
2.3.4場效遷移率(Field-effect Mobility) 15
2.3.5介面缺陷密度(Interface Trap Density, Dit) 16
2.4重要量測電性圖 17
2.4.1 ID-VG轉移特性曲線 17
2.4.2 ID-VD輸出特性曲線 18
2.4.3閘極正偏置應力(Positive Gate Bias Stress, PGBS) 18
2.4.4閘極負偏置應力(Negative Gate Bias Stress, NGBS) 19
2.4.5溫度應力(Temperature Stress) 19
第三章 熱氧化方式沉積鎢摻雜氧化銦電晶體 20
3.1製程流程圖與結構 20
3.2鎢摻雜與調變 23
3.3氧化亞氮退火處理 26
3.4遷移率 28
3.5結果與討論 30
第四章 氧電漿方式沉積鎢摻雜氧化銦電晶體 31
4.1製程流程圖與結構 31
4.2氧化銦通道層厚度選擇 34
4.3鎢摻雜與調變 37
4.4氧化亞氮退火處理 39
4.5遷移率 44
4.6材料分析 46
4.6.1原子力顯微鏡(Atomic Force Microscope, AFM) 46
4.6.2傅立葉轉換紅外光譜儀(Fourier-Transform Infrared Spectroscopy, FTIR) 48
4.6.3二次離子質譜分析儀(Secondary Ion Mass Spectrometer, SIMS) 49
4.6.4 X光繞射儀(X-ray Diffractometer, XRD) 50
4.6.5 X射線光電子能譜學(X-ray Photoelectron Spectroscopy, XPS) 51
4.7結果與討論 53
第五章 結論 56
參考文獻 57

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