臺灣博碩士論文加值系統

本研究旨在開發一個結合機率神經網路(Probabilistic Neural Network, PNN)與RISC-V的機器學習系統晶片(MLSoC)，以發揮硬體加速的優勢並具備微處理器的泛用性，實現高性能和高度客製化的機器學習應用。透過RISC-V自定義指令和中斷時序設計來優化軟硬體間的數據傳輸和處理流程，增進系統的整體運行效率。本研究採用MIAT系統設計方法論，實現高度的模組化設計，提高系統架構的靈活性。此外，為解決嵌入式系統中記憶體和運算資源達到最佳化設計，本研究提出一個可變精度神經網路開發框架，開發者可以依據需求調整精度。
實驗結果表明，所開發的MLSoC能夠在66毫秒內完成一張64x48大小的影像分割，每個像素的處理時間約為21微秒，消耗能量為0.00504mWh，顯示出系統在保持低功耗的同時，亦能提供高效的運算性能。此外，系統在處理不同精度設定下展現出良好的靈活性和準確性。
本研究提出了一個高效能、低功耗且易於擴展的機器學習軟硬體解決方案，MLSoC的設計在工業應用中尤其具有潛力，適合被廣泛應用於需要即時影像處理和物件識別的場景。本研究的成果也提供了一個實用的參考模型，有助於未來在FPGA上實現更多高效的機器學習解決方案，推動更廣泛的醫療和工業應用。

This study aims to develop a machine learning system-on-a-chip (MLSoC) that integrates a Probabilistic Neural Network (PNN) with RISC-V, leveraging the advantages of hardware acceleration while maintaining the versatility of a microprocessor to achieve high performance and highly customizable machine learning applications. The system optimizes data transfer and processing workflows between software and hardware through custom instructions and interrupt handling, enhancing overall system efficiency. The study employs the MIAT system design methodology to achieve a highly modular design, improving the flexibility of the system architecture. Additionally, to address the challenges of memory and computational resource limitations in embedded systems, this study proposes a variable precision neural network development framework, allowing developers to adjust precision according to their needs.
Experimental results show that the developed MLSoC can complete the segmentation of a 64x48 image in 66 milliseconds, with each pixel processed in approximately 21 microseconds, demonstrating that the system can provide efficient computational performance while maintaining low power consumption. Furthermore, the system exhibits good flexibility and accuracy under different precision settings.
This research provides an efficient, low-power, and scalable hardware solution for machine learning. The MLSoC design has significant potential in industrial applications, especially suitable for scenarios requiring real-time image processing and object recognition. The outcomes of this research also offer a practical reference model for other researchers, facilitating the development of more efficient machine learning solutions on FPGA, thereby advancing broader application development.

摘要............................................................ I
Abstract ...................................................... II
目錄 .......................................................... III
圖目錄 ........................................................ VI
表目錄 ........................................................ X
第一章、 緒論 ................................................. 1
1.1 研究背景 .................................................. 1
1.2 研究目的 .................................................. 3
1.3 論文架構 .................................................. 4
第二章、 技術回顧 ............................................. 5
2.1 RISC-V神經網路硬體加速器 .................................. 5
2.1.1 RISC-V起源與發展 ....................................... 5
2.1.2 RISC-V基本特點 ......................................... 5
2.1.3 RISC-V 指令集架構 ...................................... 6
2.1.4 基於RISC-V的神經網路硬體加速器軟硬體整合架構設計 ...........8
2.2 神經網路硬體加速 ......................................... 10
2.2.1 整數量化法 ............................................. 10
2.2.2 多精度神經網路 ......................................... 12
2.3 機率神經網路 ............................................. 13
2.3.1 機率神經網路 ........................................... 13
2.3.2 機率神經網路硬體加速器 .................................. 17
2.4 MIAT系統設計方法論 ....................................... 19
2.4.1 IDEF0階層式模組化設計 .................................. 20
2.4.2 GRAFCET離散事件建模 .................................... 22
2.4.3 硬體高階合成 ........................................... 25
第三章、 機率神經網路硬體加速器設計 ............................ 28
3.1 機率神經網路硬體設計 ...................................... 28
3.1.1 IDEF0 ................................................. 28
3.1.2 機率密度函數計算模組(A1) ................................ 29
3.1.3 決策模組(A2) ........................................... 32
3.1.4 Verilog硬體設計 ........................................ 35
3.2 定點數量化 ............................................... 36
3.3 可變精度設計 ............................................. 37
3.3.1 軟體可變精度設計 ....................................... 37
3.3.2 多精度硬體設計 ......................................... 39
3.4 管線化設計 ............................................... 39
3.4.1 管線化原理 ............................................. 39
3.4.2 PNN管線化設計 .......................................... 42
3.4.3 管線化的PNN Verilog設計 ................................ 45
第四章、 RISC-V機器學習系統晶片設計 ............................ 47
4.1 RISC-V處理器和開發平台硬體設計 ............................ 47
4.1.1 系統設計 ............................................... 47
4.1.2 系統中斷配置 ........................................... 49
4.2 RISC-V的PNN硬體加速器軟體設計 ............................. 52
4.2.1 RISC-V軟體IDEF0 ....................................... 52
4.2.2 系統狀態機(A1) ......................................... 53
4.2.3 Data Set狀態機(A11) ................................... 55
4.2.4 Test Feature狀態機(A12) ............................... 56
4.2.5 中斷狀態機(A14) ....................................... 57
4.3 RISC-V擴充指令設計 ...................................... 58
第五章、 RISC-V硬體加速器實驗 ................................ 61
5.1 實驗環境 ................................................ 61
5.1.1 實驗平台 .............................................. 61
5.1.2 測試資料集 ............................................ 64
5.1.3 訓練用特徵 ............................................ 65
5.2 機率神經網路硬體加速器實驗 ............................... 69
5.2.1 數位電路合成 .......................................... 69
5.2.2 時序驗證 ............................................. 71
5.2.3 比較不同Sigma測試結果 ................................. 71
5.2.4 比較不同位元精度測試結果 ............................... 72
5.3 RISC-V系統晶片實驗 ...................................... 73
5.3.1 系統狀態機測試 ........................................ 73
5.3.2 中斷觸發測試 .......................................... 74
5.3.3 並列式寫入測試 ........................................ 76
5.3.4 執行時間測試 .......................................... 79
5.3.5 實作結果 .............................................. 80
5.3.6 硬體加速器綜合評比 ..................................... 81
第六章、 結論與未來展望 ...................................... 85
6.1 結論 .................................................... 85
6.2 未來展望 ................................................ 86
第七章、 參考文獻 ............................................ 87

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