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研究生:黃仕成
研究生(外文):Shih-Cheng Huang
論文名稱:使用擺置後的設計特徵及極限梯度提升演算法預測繞線後的繞線需求
論文名稱(外文):Routing Demand Prediction Using Placement Features with Extreme Gradient Boosting
指導教授:陳聿廣
指導教授(外文):Yu-Guang Chang
學位類別:碩士
校院名稱:國立中央大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2023
畢業學年度:112
語文別:中文
論文頁數:36
中文關鍵詞:極限梯度提升
外文關鍵詞:extreme gradient boosting
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隨著現代半導體製程工藝的進步,在相同面積下能容納更多的電晶體的數量,而晶片設計的複雜度也相應變高,在這些影響下,設計積體電路所需要花費的時間也變得十分可觀。其中在物理設計(Physical design)的流程中繞線就是十分費時的步驟之一,在大多數情況下繞線會花費數小時甚至數天。然而在某些情況下會發生像是繞線擁擠,或是違反設計規則檢查(Design rule check)的狀況發生,當這些狀況發生時,我們需要回到流程的前幾個步驟修正晶片中的問題再重新繞線一次。然而在晶片設計的週期中這樣的狀況會反覆執行數次,進而延誤了晶片下線(Tapeout)的進度。因此許多研究利用機器學習的演算法來建構模型,提前幾個階段預測後續可能會遇到的問題,幫助工程師提前解決問題,減少反覆的執行繞線流程。例如預測晶片繞線後,哪些區域會有繞線擁擠,或是預測哪些區域會有違反晶片設計規範的問題。在這些研究領域多數使用了神經網路的模型架構,然而在訓練神經網路需要花費大量的計算時間,此外為了避免過度凝合(Overfitting)在訓練神經網路需要大量的訓練資料,但因為晶片的設計流程十分花費時間,要收集到充足的訓練資料要花費大量時間成本。因此在本篇論文中使用了整體學習(Ensemble learning)的演算法,極限梯度提升(Extreme gradient boosting, XGBoost),極限梯度提升是一種高效率的演算法,並且相較於傳統的梯度提升極限梯度提升在其目標函數加入了正則化項,這在少量的訓練資料下可以避免過度凝合,使得模型在有限的訓練資料下可以準確的預測出繞線結果,此外極限梯度提升是基於決策樹的架構,相較於神經網路有較佳的解釋性。藉由以上極限梯度提升的優點,本篇論文分析了各種輸入特徵的重要性,並且篩選掉多餘的特徵,以減少訓練時間及提升模型在推理時的效率,在訓練模型時,我們提取晶片擺置後的電路特徵,以及提取繞線過後的繞線需求當作預測目標。
With the advancement of semiconductor manufacturing techniques, more transistors can be accommodated in the same area. As the results, the complexity of Integrated Circuits (ICs) increases. Consequently, designing ICs has become notably time consuming. Among the various stages, routing, in particular, is one of the most time-consuming steps in the physical design process, often taking several hours or even days. In some cases, issues such as routing congestion or Design Rule Violations (DRVs) occur. When these issues arise, it necessitates returning to earlier stages of the process to adjust the chip design to fix these issues. This iterative process may occur multiple times throughout the chip design cycle. Hence, many studies employ machine learning algorithms to construct models that can predict potential issues in previous stages. Engineers can adjust chip design before actually performing routing, reducing the repeated execution of the routing process. However, due to the process of chip design is time consuming, it’s hard to collect a vast amount of training data. Moreover, Neural Network (NN) base model needs a lot of data for model training, insufficient training data might lead to overfitting. Therefore, this paper utilizes the ensemble learning algorithm, Extreme Gradient Boosting (XGBoost). XGBoost is a highly efficient algorithm, and compared to traditional gradient boosting methods, XGBoost incorporates regularization term into its objective function. This regularization term can prevent overfitting, enabling the model to predict routing outcomes accurately with limited training data. Additionally, XGBoost is based on a decision tree structure, offering better interpretability compared to neural networks. Leveraging these advantages of XGBoost, this paper analyzes the importance of input features, filtering out redundant features to reduce training time and boost model efficiency during inference. During model training, we extract circuit features in placement stage and use the routing demand after global routing as the prediction target. 
中文摘要 i
Abstract ii
致謝 iv
Table of Contests v
Table of Figures vi
Table of Tables vii
Chapter 1 Introduction 1
Chapter 2 Background and Relate Works 4
2.1 Physical design flow 4
2.2 Routing congestion and design rule violations 5
2.3 CNN and FCN 5
2.4 Extreme gradient boosting (XGBoost) 7
Chapter 3 Proposed Methodology 9
3.1 XGBoost based routing demand prediction framework 9
3.2 Grid-based placement features 10
Chapter 4 Experimental results 14
4.1 Experiment setup and benchmark 14
4.2 Feature importance analysis 15
4.3 Prediction performance comparison 18
Chapter 5 Conclusions 24
Chapter 6 Reference 25
[1]. Tianqi Chen and Carlos Guestrin. Xgboost: A scalable tree boosting system. In Proceedings of the 22Nd ACM SIGKDD International Conference on Knowledge Discovery and Data Mining, KDD ’16, pages 785–794, New York, NY, USA, 2016. ACM.
[2]. A. F. Tabrizi et al., "A Machine Learning Framework to Identify Detailed Routing Short Violations from a Placed Netlist," 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, 2018, pp. 1-6
[3]. Z. Xie et al., "RouteNet: Routability prediction for Mixed-Size Designs Using Convolutional Neural Network," 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Diego, CA, USA, 2018
[4]. Z. Zhou et al., "Congestion-aware Global Routing using Deep Convolutional Generative Adversarial Networks," 2019 ACM/IEEE 1st Workshop on Machine Learning for CAD (MLCAD), Canmore, AB, Canada, 2019, pp. 1-6
[5]. Y. -H. Huang et al., "Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model," 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), Florence, Italy, 2019, pp. 180-185
[6]. W. Zeng, A. Davoodi and R. O. Topaloglu, "Explainable DRC Hotspot Prediction with Random Forest and SHAP Tree Explainer," 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, 2020, pp. 1151-1156
[7]. C. Ma, Y. Xiao, S. Wang, J. Yu and J. Chen, "CongestNN: An Bi-Directional Congestion Prediction Framework for Large-Scale Heterogeneous FPGAs," 2021 IEEE 14th International Conference on ASIC (ASICON), Kunming, China, 2021, pp. 1-4
[8]. D. Kim, H. Kwon, S. -Y. Lee, S. Kim, M. Woo and S. Kang, "Machine Learning Framework for Early Routability Prediction with Artificial Netlist Generator," 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, 2021, pp. 1809-1814
[9]. S. Liu, Q. Sun, P. Liao, Y. Lin and B. Yu, "Global Placement with Deep Learning-Enabled Explicit Routability Optimization," 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, 2021, pp. 1821-1824
[10]. Y. -Y. Huang, C. -T. Lin, W. -L. Liang and H. -M. Chen, "Learning Based Placement Refinement to Reduce DRC Short Violations," 2021 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, 2021, pp. 1-4
[11]. M. Su et al., "High-Correlation 3D Routability Estimation for Congestion-guided Global Routing," 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), Taipei, Taiwan, 2022, pp. 580-585
[12]. J.G. Lin et al, "DRC Violation Prediction with Pre-global-routing Features Through Convolutional Neural Network," in GLSVLSI '23: Proceedings of the Great Lakes Symposium on VLSI, pages 313–319, Knoxville TN USA, 2023
[13]. M. Rapp et al., "MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 10, pp. 3162-3181
[14]. Cadence, Inc. Innovus Implementation System.https://www.cadence.com/en_US/home/tools/digital-design-andsignoff/soc-implementation-and-floorplanning/innovus-implementationsystem.html
[15]. “dmlc XGBoost stable”, https://xgboost.readthedocs.io/en/stable/index.html
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