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研究生:林慧昇
研究生(外文):Hui-Sheng Lin
論文名稱:晶圓圖之網格及稀疏缺陷樣態辨識
論文名稱(外文):Recognizing Grid and Sparse Defect Patterns on Wafer Maps
指導教授:陳聿廣陳竹一梁新聰梁新聰引用關係
學位類別:碩士
校院名稱:國立中央大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2023
畢業學年度:112
語文別:中文
論文頁數:67
中文關鍵詞:晶圓圖網格缺陷樣態稀疏缺陷樣態
外文關鍵詞:WAFER MAPGRID DEFECT PATTERNSPARSE DEFECT PATTERN
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隨著晶圓製造成本的不斷增加,控制晶圓良率變得至關重要。達成此目標的其中一種有效方法是分析晶圓圖中的缺陷樣態,然而幾乎所有研究都集中在聚類分佈的缺陷樣態上,相反的,本文致力於分析反聚類分佈的缺陷樣態。我們提出了對這些缺陷樣態進行標記和分類的方法,我們將反聚類分佈缺陷樣態分為兩種類型:Grid及Sparse。在Grid缺陷樣態中,缺陷晶片在晶圓上呈現規則分佈,而在Sparse缺陷樣態中,缺陷晶片在晶圓上呈現離散式分布。
我們的方法由三個階段組成。 在第一階段,我們對晶圓圖進行預處理,去除可能干擾Grid缺陷樣態識別的群聚和線狀缺陷樣態。接下來,我們從晶圓圖中提取相關特徵參數並進行綜合分析來識別Grid缺陷樣態,其中可能包含多種類型的缺陷樣態。在第二階段,我們採用預先建立的隨機缺陷模型來確定晶圓圖中的缺陷是否表現出反聚類分佈。 隨機缺陷模型中包括三種類型:Score、Discrete die和Under 2-die 模型。通過應用這些模型並在晶圓圖上進行加權計算,我們可以分析出缺陷樣態的分佈類型。如果缺陷樣態表現出反聚類分佈,則它們會進入第三階段。最後,我們從晶圓圖中提取特徵參數並分析它們是否具有特殊的Grid或Sparse缺陷樣態。
為了驗證我們的方法,我們在真實晶圓資料集上進行了實驗,並實現了高準確度的辨識結果。實驗結果證明了我們的方法在辨識和分類反聚類分佈缺陷樣態的有效性和可靠性。
With the increasing cost of wafer manufacturing, it has become crucial to control wafer yield. Analyzing defect patterns of wafer maps is an effective method to achieve this goal. While many studies have focused on defect patterns with cluster distributions, this thesis addresses the analysis of anti-cluster distribution defect patterns. We propose a method to label and classify these patterns. We classify anti-cluster distribution defect patterns into two types: Grid and Sparse. For the Grid pattern, defect dies exhibit a regular distribution across the wafer, while for the Sparse pattern, defect dies are dispersed across the wafer.
Our method consists of three stages. In the first stage, we preprocess the wafer maps to remove cluster and line defect patterns that may interfere with the identification of Grid patterns. Next, we extract relevant features from the wafer maps and perform comprehensive analysis to identify Grid patterns, which may contain multiple types of defect patterns. In the second stage, we employ pre-established random defect models to determine whether the defects on the wafer maps exhibit an anti-cluster distribution. The random defect models include three types: Score, Discrete die, and Under 2-die models. By applying these models and employing weighted calculations on the wafer maps, we can analyze and determine the distribution type of the defect patterns. If the patterns demonstrate an anti-cluster distribution, they progress to the next stage. Finally, we extract features from the wafer maps and analyze them to determine if they represent specific Grid or Sparse patterns.
To validate our approach, we conducted experiments on real wafers and achieved a high accuracy of recognition. Experimental results demonstrate the effectiveness and reliability of our method in identifying and classifying anti-cluster distribution defect patterns.
摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vi
表目錄 viii
第一章 緒論 1
1.1 前言 1
1.2 研究動機 2
1.3 論文貢獻 2
1.4 論文架構 3
第二章 文獻探討與預備知識 4
2.1 不同晶圓缺陷樣態對應的製程錯誤 4
2.2 利用隨機性對晶圓分群 5
2.3 機器學習辨識TSMC九種缺陷樣態 5
2.3 利用特徵提取辨識晶圓多重樣態 7
2.4 尚未被識別之缺陷樣態 8
2.5 網格線或平行線狀Grid缺陷樣態 10
2.6 聚類演算法DBSCAN 11
2.7 特徵提取辨識Grid缺陷樣態 13
第三章 反聚類缺陷樣態晶圓辨識 14
3.1 缺陷樣態 14
3.1.1 九種缺陷樣態以及徵狀性分類 14
3.1.2 有徵狀性缺陷樣態之聚類(Cluster)與反聚類(Anti-cluster)缺陷樣態 15
3.1.3 Grid缺陷樣態 16
3.1.4 Sparse缺陷樣態 17
3.2 Grid與Sparse缺陷樣態辨識架構與流程簡要 18
3.3 Mode Selection 19
3.4 DBSCAN 1 20
3.5 Remove Lines 24
3.6 Grid Recognition 1 25
3.7 DBSCAN 2 32
3.8 Random Defect Models 33
3.9 Cluster Classification 37
3.9.1 Weighted calculation 37
3.9.2 Cluster Classification 42
3.10 Grid Recognition 2 43
3.11 Sparse Recognition 45
第四章 實驗結果與分析 46
4.1 軟硬體版本與設備 46
4.2 反聚類缺陷樣態晶圓之標籤 46
4.2.1標籤數量 46
4.2.2 Grid標籤 47
4.2.3 Salient Grid標籤分類 47
4.2.4 Possible Grid標籤範例 49
4.2.5 Sparse標籤 50
4.3本篇架構辨識準確度與分析 51
4.3.1 Grid缺陷樣態辨識準確度 51
4.3.2 辨識之None Grid晶圓分析 52
4.4 不同mode下對應時間差異 52
第五章 結論 53
參考文獻 54
[1]Mill-Jer Wang, Yen-Shung Chang, J.E. Chen, Yung-Yuan Chen, and Shaw-Cherng Shyu, “Yield Improvement by Test Error Cancellation,” in Proceedings of the Fifth Asian Test Symposium (ATS'96), pp. 258-262, Nov. 1996.
[2]Jwu-E Chen, Tung-Ying Lu, and Hsing-Chung Liang, “Testing the Spatial Pattern Randomness on Wafer Maps,” in Proc. VLSI Test Technology Workshop (VTTW), 5 pages, July 2019.
[3]M. Wu, J. R. Jang and J. Chen, "Wafer Map Failure Pattern Recognition and Similarity Ranking for Large-Scale Data Sets," IEEE Transactions on Semiconductor Manufacturing, vol. 28, no. 1, pp. 1-12, Feb. 2015.
[4]Cheng Hao Jin, Hyuk Jun Na, Minghao Piao, Gouchol Pok and Keun Ho Ryu, "A Novel DBSCAN-Based Defect Pattern Detection and Classification Framework for Wafer Bin Map," IEEE Transactions on Semiconductor Manufacturing, Vol. 32, No. 3, pp.286-292, August 2019.
[5]M. Nero, C. Shan, L. -C. Wang and N. Sumikawa, "Concept Recognition in Production Yield Data Analytics," in Proc. 2018 IEEE International Test Conference (ITC), paper 9.3, 10 pages, 2018.
[6]P. Y. -Y. Liao et al., "WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques," in Proc. 2021 IEEE International Test Conference (ITC), 2021, pp. 309-313
[7]Tung-Ying Lu, "Application of Wafer Map Partition Analysis to Enhance the Salient Pattern Identification", Master’s Thesis, National Central University, Oct. 2019.
[8]Yung-Lin Lin, "Feature-based Grid Pattern Classification in Wafer Map Analysis", Master’s Thesis, National Central University, Jul. 2022.
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