臺灣博碩士論文加值系統

隨著半導體製程的進步，電路老化的問題變得日益突出。其中一種最嚴重的老化效應是負偏溫度不穩定性（NBTI），它會增加PMOS晶體管的閾值電壓和傳播延遲。增加的延遲在長時間下可能導致時序違規，甚至系統故障。為了改善NBTI帶來的問題，提出了一些老化緩解方法，如內部節點控制（INC）和輸入向量控制（IVC）。INC應用特殊設計的邏輯門來緩解老化效應，而IVC則在電路閒置期間使用適當的輸入向量來防止NBTI造成的壓力。然而，INC會導致額外的面積成本和功耗，而電路的結構會限制了IVC的可控性。儘管過去提出了各種基於INC或IVC的老化容忍方法，但只有少數作者有考慮兩種方法之間的協同優化。在本文中，我們介紹了一種基於GNN的INC和IVC協同優化框架，充分利用這兩種方法的優勢，盡可能地降低老化引起的延遲。我們的做法是使用經過良好訓練的GNN來識別電路中受到嚴重老化影響的邏輯閘，然後在給定面積限制下使用INC和IVC來緩解老化效應。實驗結果表示，在電路中採用我們的方法，與先前的研究成果相比，我們可以降低因老化造成額外的傳遞時間延遲大約2.16倍，同時，我們與先前的研究相較之下，我們只需要29.5%額外的面積消耗。此外，我們的方法執行時間也比先前的做法還要少，加快了2.6倍的速度。

With the advancement of semiconductor processes, the issue of circuit aging is becoming increasingly prominent. One of the most severe aging effects is negative bias temperature instability (NBTI), which increases the threshold voltage and propagation delay of PMOS transistors. Over time, the increased delay may lead to timing violations and even system failures. To address the problems caused by NBTI, various aging mitigation techniques have been proposed, such as Internal Node Control (INC) and Input Vector Control (IVC). INC applies specially designed logic gates to mitigate aging effects, while IVC utilizes appropriate input vectors during circuit idle periods to alleviate the pressure from NBTI. However, INC incurs additional area costs and power consumption, while the structure of the circuit limits the controllability of IVC. Although various aging tolerance methods based on INC or IVC have been proposed in the past, only a few authors have considered the synergistic optimization between the two methods. In this thesis, we introduce a GNN-based INC and IVC co-optimization framework, leveraging the advantages of both methods to minimize aging-induced delays as much as possible. Our approach involves using a well-trained GNN to identify logic gates in the circuit significantly affected by aging, and then utilizing INC and IVC under given area constraints to mitigate aging effects. Experimental results indicate that adopting our method in the circuit can reduce additional propagation delay caused by aging by approximately 2.16 times compared to previous research results, while requiring only 29.5% additional area consumption compared to previous studies. Furthermore, the execution time of our method is also faster, accelerating by 2.6 times compared to previous approaches.

摘要 i
Abstract ii
致謝 iii
Table of Contents iv
Table of Figures vi
Table of Tables viii
Chapter 1 Introduction 1
1.1 Aging Issues 1
1.2 Mitigation Methods 2
1.3 Contributions 4
Chapter 2 Preliminaries 6
2.1 Aging Effect and Aging Model 6
2.2 Aging Mitigation Methods 7
2.2.1 Internal Node Control (INC) 7
2.2.2 Input Vector Control (IVC) 8
2.3 Graph Neural Network (GNN) for Electronic Design Automation (EDA) 9
2.3.1 Graph Neural Network (GNN) 10
2.3.2 GNN-Based Approaches for Mitigating Aging Issues 13
Chapter 3 Problem Formulation 15
3.1 Motivation 15
3.2 Problem Formulation 16
Chapter 4 GNN-Based INC and IVC Co-Optimization Framework for Aging Mitigation 17
4.1 Overall Framework 17
4.2 GNN-based Approach for INC Logic Deployment 18
4.3 GNN-based Co-Optimization with INC and IVC 21
4.4 Iterative GNN-based Co-Optimization with INC and IVC 22
Chapter 5 Experimental Results 25
5.1 Experimental Setting 25
5.2 Comparison of Aging-induced Degradation Improvement Rate (Dimp) 27
5.3 Comparison of Gate Replacement Rate 28
5.4 Comparison of Area Overhead (Ainc) 29
5.5 Comparison of Ratio of Delay Improvement over Area Overhead (Dimp/Ainc) 30
5.6 Comparison of Execution Time 31
5.7 Comparison of Leakage Power 33
Chapter 6 Conclusions 34
Reference 35

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