臺灣博碩士論文加值系統

本論文採用 TSMC 0.18μm製程，提出了一種基於兩步單斜率(Two-Step Single-Slope)類比數位轉換器應用的高動態範圍CMOS影像感測器，全電路架構主要分成三個部分，第一部分像素陣列為接收光源的感應端，像素電路能根據接收到的光照強度，產生不同大小的光電流，架構採用線性-對數型主動式像素感測器為基底做改良，此架構增加了在光電流較弱下，感應端電壓值的下降速率，加快了像素單元的運作時間，與改良前的架構相比，有更高的動態範圍(Dynamic Range)，且因架構複雜度較低，擁有較高的填充係數(Fill Factor)，可達51%；第二部分為可程式化增益放大器(PGA)，會將前一級像素陣列所產生的電壓訊號做大，確保像素電壓的大小會符合後端接收電路的輸入範圍，提高電路的精準度，與傳統的PGA架構相比，新增加了通過動態比較器與帶差參考電壓電路組成的增益選擇控制電路，可以實現自動判別所需要的放大倍率，最後透過交換電容式放大器將輸入訊號做放大，其擁有1倍、2倍、4倍及8倍4種不同的放大倍率；第三部分為類比數位轉換器(ADC)，可以將接收到的訊號轉換成數位訊號輸出，本篇論文所使用的架構為兩步單斜率類比數位轉換器(Two-Step Single-Slope ADC)，轉換過程分為M bit粗略(coarse)轉換和N bit 精細(fine) 轉換，以產生總bit (T-bit) 的分辨率，架構上使用比較器、計數器及多個開關組成，由於架構簡單，減省了面積消耗，且相較於傳統的單斜率(Single-Slope )ADC架構有較少的轉換週期，提升了整體的轉換效率，在取樣頻率1 MHz的設計下，輸出總位元為8bit，ENOB達到7.511 bit，其INL及DNL皆小於 1。

This thesis proposes a high dynamic range CMOS image sensor based on a Two-Step Single-Slope analog-to-digital converter using the TSMC 0.18μm process. The overall circuit architecture is mainly divided into three parts. The first part, the pixel array, serves as the sensing terminal for receiving light sources. The pixel circuit generates photocurrents of varying magnitudes according to the intensity of the received light. The architecture is an improved version of a linear-logarithmic active pixel sensor. This design increases the rate at which the sensing terminal voltage decreases under weaker photocurrent, accelerating the operation time of the pixel units. Compared to the previous architecture, it has a higher dynamic range and, due to the lower complexity of the structure, achieves a higher fill factor of up to 51%.
The second part is the programmable gain amplifier (PGA), which amplifies the voltage signal generated by the preceding pixel array to ensure that the pixel voltage falls within the input range of the subsequent receiving circuit, thus improving the circuit''s accuracy. Compared to traditional PGA structures, it includes a gain selection control circuit composed of a dynamic comparator and a bandgap reference voltage circuit, which enables automatic determination of the required amplification factor. The input signal is then amplified through a switched-capacitor amplifier, providing four different amplification factors: 1x, 2x, 4x, and 8x.
The third part is the analog-to-digital converter (ADC), which converts the received signal into a digital output. The architecture used in this thesis is a Two-Step Single-Slope ADC. The conversion process is divided into an M-bit coarse conversion and an N-bit fine conversion to achieve a total bit (T-bit) resolution. The architecture includes a comparator, a counter, and several switches. Due to its simplicity, it reduces area consumption and, compared to traditional Single-Slope ADC architectures, has fewer conversion cycles, thereby improving overall conversion efficiency. Under a sampling frequency of 1 MHz, the total output bits are 8 bits, the effective number of bits (ENOB) reaches 7.511 bits, and both the integral non-linearity (INL) and differential non-linearity (DNL) are less than 1.

論文審定書 i
摘要 ii
Abstract iii
目錄 v
圖次 viii
表次 ix
第1章 概論 1
1.1 研究動機 1
1.2 章節介紹 3
第2章 CMOS影像感測器架構介紹 4
2.1 感光元件 6
2.1.1 CCD影像感測器 6
2.1.2 CMOS影像感測器 7
2.2 像素電路特性參數介紹 10
2.2.1 動態範圍(Dynamic Range) 10
2.2.2 填充係數(Fill Factor) 11
2.3 可程式增益放大器(PGA) 11
2.4 類比數位轉換器(ADC) 13
2.5 文獻回顧 16
第3章 CMOS影像感測器全電路設計實現 17
3.1 像素架構 19
3.1.1 線性-對數型主動式架構 19
3.1.2 新式線性-對數型主動式像素架構 20
3.2 列解碼器 22
3.3 Interface介面 24
3.4 計數器 24
3.5 PGA 26
3.5.1 PGA整體架構 26
3.5.2 帶差參考電壓電路 26
3.5.3 增益選擇控制電路 28
3.5.4 動態比較器 30
3.5.5 交換電容式放大器 31
3.5.6 摺疊疊接式運算放大器 31
3.6 Two Step Single Slope ADC 33
3.6.1 傳統單斜率(Single Slope) ADC架構 33
3.6.2 兩步單斜率(Two Step Single Slope) ADC架構 34
第4章 模擬結果 36
4.1 全電路佈局 36
4.2 像素電路模擬 38
4.2.1 動態範圍模擬 40
4.3 PGA模擬 42
4.3.1 動態比較器模擬 42
4.3.2 PGA全電路模擬 43
4.4 Two Step Single-Slope ADC模擬 45
4.4.1 靜態參數模擬結果 47
4.4.2 動態參數模擬結果 48
4.5 量測方法 49
4.6 電路規格與文獻比較 53
4.6.1 電路規格 53
4.6.2 文獻比較 54
第5章 結論與未來展望 55
5.1 結論 55
5.2 未來展望 56
參考文獻 56

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