臺灣博碩士論文加值系統

本論文完成之高性能類比數位轉換器(ADC)，可以達到高速兼顧高解析度、及低功率消耗之特性。基於低功耗目的，採用連續漸進式(SAR ADC)之架構使其能在低電源電壓下運作，並結合基於時域比較器的時域量化架構，以突破傳統型架構在先進製程下因電晶體本質增益下降、製程本身的偏移變大以及供應電壓下降而產生的設計瓶頸。
在時域比較器中，使用了以壓控振盪器(VCO)為基礎所設計的電壓時間轉換器，藉此來獲得電路穩定與低雜訊影響的好處，並將其改良，在壓控振盪器之輸出端加入了SR時域放大器，使其相位差得以指數型的方式成長，與傳統的線性型成長相比，可以更加快速地脫離相位偵測器(Phase detector)的死區(dead zone)，以克服傳統VCO比較器在追求高分辨率時在速度上所遇到的瓶頸，並因應改良後的電壓時間轉換器，改變了相位偵測器之操作模式，使其能夠應用於新型電壓時間轉換器所產生的輸出。
在採樣開關的部分，使用了改良式的的低功耗自舉式開關，藉由將傳統式的架構加以簡化，使其能以較低的功耗，來獲得更加穩定與可靠的採樣訊號。在切換方式的部分則採用了單調式切換(Monotonic)的方法，藉此來降低整體功耗與面積。
此論文在TSMC 40nm的製程下，完成一個10位元，轉換速率為10MS/s，供應電源為0.9V，功率消耗為57.9µW，ENOB為9.88bit、SFDR為74.07dB，FoM達6.14(fJ/conv.-step)的SAR ADC。

The high-performance analog-to-digital converter (ADC) developed in this thesis achieves high speed, high resolution, and low power consumption. To achieve low power consumption, a successive approximation register (SAR) ADC architecture is employed, allowing it to operate at low supply voltage. This is combined with a time-domain quantization architecture based on a time-domain comparator to overcome the design bottlenecks caused by the reduced intrinsic gain of transistors, increased process variation, and decreased supply voltage in advanced processes.
In the time-domain comparator, a voltage-to-time converter based on a voltage-controlled oscillator (VCO) is used, providing the benefits of circuit stability and low noise impact. This design is further improved by adding an SR time amplifier at the VCO output, allowing the phase difference to grow exponentially. Compared to traditional linear growth, this enables faster escape from the dead zone of the phase detector, solving the issue between high resolution and high speed in traditional VCO comparators. To accommodate the output generated by the improved voltage-to-time converter, the operation mode of the phase detector is modified, enabling it to be applied to the new voltage-to-time converter output.
For the sampling switch, an improved low-power bootstrap switch is used. By simplifying the traditional architecture, it achieves more stable and reliable sampling signals with lower power consumption. In terms of switching method, a monotonic switching is adopted to reduce overall power consumption and area.
This thesis presents a 10-bit SAR ADC in TSMC 40nm process, with a conversion rate of 10MS/s, a supply voltage of 0.9V, power consumption of 57.9µW, an ENOB of 9.88 bits, an SFDR of 74.07dB, and a FoM of 6.14 fJ/conv.-step.

論文審定書i
摘要ii
Abstractiii
目錄v
圖次vii
表次x
第1章 緒論1
1.1 研究動機1
1.2 論文組織架構4
第2章 研究背景介紹5
2.1 主流ADC架構介紹5
2.1.1 快閃式類比數位轉換器5
2.1.2 管線式類比數位轉換器6
2.1.3 積分三角式類比數位轉換器8
2.1.4 連續漸進式類比數位轉換器9
2.2 電壓–時間類比數位轉換器架構與發展方向簡介12
第3章 電路架構設計與介紹15
3.1 主電路架構15
3.2 各子電路之設計17
3.2.1 時域比較器17
3.2.2 採樣保持電路24
3.2.3 二進制電容陣列與單調式切換架構27
3.2.4 非同步SAR 控制邏輯32
第4章 子電路佈局與模擬34
4.1 比較器佈局與模擬34
4.1.1 比較器之模擬與比較34
4.1.2 比較器之佈局與模擬37
4.2 採樣保持電路佈局與模擬40
4.2.1 採樣保持電路模擬40
4.2.2 採樣保持電路佈局與模擬41
4.3 時脈產生器佈局與模擬44
4.3.1 時脈產生器模擬44
4.3.2 時脈產生器佈局與模擬45
4.4 電容陣列與切換開關佈局與模擬45
4.4.1 單調式切換模擬45
4.4.2 電容陣列與切換開關佈局與模擬46
第5章 全電路佈局與模擬47
5.1 全電路佈局與模擬47
5.1.1 全電路之模擬47
5.1.2 全電路佈局48
5.1.3 全電路佈局模擬結果50
5.2 相關論文效能比較54
第6章 結論與未來展望55
6.1 結論55
6.2 未來展望56
參考文獻57

[1]B. Murmann, "ADC Performance Survey 1997-2024," [Online]. Available: https://github.com/bmurmann/ADC-survey.
[2]P. Harpe, "Successive Approximation Analog-to-Digital Converters: Improving Power Efficiency and Conversion Speed," in IEEE Solid-State Circuits Magazine, vol. 8, no. 4, pp. 64-73, Fall 2016.
[3]Y. Zhang and Z. Zhu, "Recent Advances and Trends in Voltage-Time Domain Hybrid ADCs," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 6, pp. 2575-2580, June 2022.
[4]S. Ur Rehman, M. M. Khafaji, C. Carta and F. Ellinger, "A 16 mW 250 ps Double-Hit-Resolution Input-Sampled Time-to-Digital Converter in 45-nm CMOS," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 5, pp. 562-566, May 2018.
[5]K. Gammoh, C. K. Peterson, D. A. Penry and S. -H. W. Chiang, "Linearity Theory of Stochastic Phase-Interpolation Time-to-Digital Converter," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 12, pp. 4348-4359, Dec. 2020.
[6]Chithra and N. Krishnapura, "A Flexible 18-Channel Multi-Hit Time-to-Digital Converter for Trigger-Based Data Acquisition Systems," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 6, pp. 1892-1901, June 2020.
[7]R. B. Staszewski, S. Vemulapalli, P. Vallur, J. Wallberg and P. T. Balsara, "1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 3, pp. 220-224, March 2006.
[8]G. Li, Y. M. Tousi, A. Hassibi and E. Afshari, "Delay-Line-Based Analog-to-Digital Converters," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 56, no. 6, pp. 464-468, June 2009, doi.
[9]B. Markovic, S. Tisa, F. A. Villa, A. Tosi and F. Zappa, "A High-Linearity, 17 ps Precision Time-to-Digital Converter Based on a Single-Stage Vernier Delay Loop Fine Interpolation," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 3, pp. 557-569, March 2013.
[10]N. U. Andersson and M. Vesterbacka, "A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 61, no. 10, pp. 773-777, Oct. 2014.
[11]A. Shikata, R. Sekimoto, T. Kuroda and H. Ishikuro, "A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 47, no. 4, pp. 1022-1030, April 2012.
[12]Y. -S. Shu, "A 6b 3GS/s 11mW fully dynamic flash ADC in 40nm CMOS with reduced number of comparators," 2012 Symposium on VLSI Circuits (VLSIC), Honolulu, HI, USA, 2012, pp. 26-27.
[13]J. Luo et al., "A Low Voltage and Low Power 10-bit Non-Binary 2b/Cycle Time and Voltage Based SAR ADC," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 4, pp. 1136-1148, April 2020.
[14]D. -K. Jung, K. Seong, J. -S. Han, Y. Shim and K. -H. Baek, "A 0.5 V 10 b 3 MS/s 2-Then-1b/Cycle SAR ADC With Digital-Based Time-Domain Reference and Dual-Mode Comparator," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 3, pp. 909-913, March 2022.
[15]A. Agnes, E. Bonizzoni, P. Malcovati and F. Maloberti, "A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time-Domain Comparator," 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, San Francisco, CA, USA, 2008, pp. 246-610.
[16]S. -K. Lee, S. -J. Park, H. -J. Park and J. -Y. Sim, "A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface," in IEEE Journal of Solid-State Circuits, vol. 46, no. 3, pp. 651-659, March 2011.
[17]X. Zhou, X. Gui, M. Gusev, N. Ackovska, Y. Zhang and L. Geng, "A 12-Bit 20-kS/s 640-nW SAR ADC With a VCDL-Based Open-Loop Time-Domain Comparator," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 2, pp. 359-363, Feb. 2022.
[18]Y. Kim and C. Yoo, "A 100-kS/s 8.3-ENOB 1.7- uW Time-Domain Analog-to-Digital Converter," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 61, no. 6, pp. 408-412, June 2014.
[19]K. Yoshioka, "VCO-Based Comparator: A Fully Adaptive Noise Scaling Comparator for High-Precision and Low-Power SAR ADCs," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 12, pp. 2143-2152, Dec. 2021.
[20]Z. Ding, X. Zhou and Q. Li, "A 0.5–1.1-V Adaptive Bypassing SAR ADC Utilizing the Oscillation-Cycle Information of a VCO-Based Comparator," in IEEE Journal of Solid-State Circuits, vol. 54, no. 4, pp. 968-977, April 2019.
[21]J. Li, X. Liu, J. Liu, D. Zhao, W. Yan and C. Bi, "Design of a High-Precision Time-Domain Comparator," 2019 IEEE 13th International Conference on Anti-counterfeiting, Security, and Identification (ASID), Xiamen, China, 2019, pp. 239-243.
[22]B. L. Tong, X. F. Zhou, “A Linear Range Expansion Technique for Time Amplifier," Journal of Fudan University (Natural Science), vol. 4, no. 6, pp. 725-732, 2010.
[23]T. B. Nazzal and S. A. Mahmoud, "Low-power bootstrapped sample and hold circuit for analog-to-digital converters," 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), Abu Dhabi, United Arab Emirates, 2016, pp. 1-4.
[24]C. -C. Liu, S. -J. Chang, G. -Y. Huang and Y. -Z. Lin, "A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure," in IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 731-740, April 2010.
[25]B. P. Ginsburg and A. P. Chandrakasan, "500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC," in IEEE Journal of Solid-State Circuits, vol. 42, no. 4, pp. 739-747, April 2007.
[26]You-Kuang Chang, Chao-Shiun Wang and Chorng-Kuang Wang, "A 8-bit 500-KS/s low power SAR ADC for bio-medical applications," 2007 IEEE Asian Solid-State Circuits Conference, Jeju, Korea (South), 2007, pp. 228-231.