臺灣博碩士論文加值系統

本論文提出一顆供應電壓為0.5伏特，每秒五百萬次取樣之低功耗十位元連續漸進式類比數位轉換器(SAR ADC)。由於連續漸進式架構大多搭配電容式數位類比轉換器(CDAC)，而其所引入的劣勢便是功耗及面積，因此本論文採用自適應重置(Adaptive-reset)切換方式來減輕上述問題，該切換方式相對於傳統切換方式減少了90%的CDAC平均切換能量，且該切換方式於SAR轉換期間的共模電壓保持不變，能夠放寬比較器的設計。此外，相較於傳統的設計，本設計採用基於壓控振盪器(VCO)架構之時域比較器，該比較器能夠根據輸入電壓差自適應地調整其雜訊性能，通過利用此種特性，減少了比較器所需花費之功耗。藉由結合上述優勢，提高整體SAR ADC之能源效率。

本論文使用TSMC 40nm 1P9M CMOS製程實現，核心面積為0.044 mm^2，供應電壓為0.5 V、取樣頻率為每秒五百萬次、在輸入信號接近奈奎斯特頻率下，微分非線性誤差 (DNL) 為0.251/-0.249 LSB，積分非線性誤差 (INL) 為0.265/-0.197 LSB，信號失真比 (SNDR) 為60.484 dB，無雜散動態範圍 (SFDR) 為73.418 dB，有效位元數 (ENOB) 為 9.755 bit，平均功耗為19.3 uW，FoM 為 4.47(fJ/conv-step) 。

This paper presents a 10-bit low power SAR ADC operating at a supply voltage of 0.5 volts with a sampling rate of five million samples per second. Traditional SAR architectures typically employ CDAC, which are known to introduce disadvantages in terms of power consumption and area . To address these issues, this study employs an Adaptive-Reset switching scheme, mitigating the aforementioned drawbacks. This switching scheme reduces the average switching energy of the CDAC by 90% compared to the traditional scheme. Furthermore, the switching scheme maintains a constant common-mode voltage during the SAR conversion, which can relax the design requirements of the comparator. In addition, distinct from conventional design, this design employs a time-domain comparator based on VCO structure. This comparator can adaptively adjust its noise performance according to the input voltage difference, thereby reducing the power consumption required by the comparator. By combining the aforementioned advantages, the overall energy efficiency of the SAR ADC is improved.

This work uses the TSMC 40nm 1P9M CMOS process, and the core area is 0.044 mm^2. The supply voltage is 0.5 V, sampling rate is 5 MHz. When tested with input signals approaching the Nyquist frequency, the ADC achieves a DNL error of +0.251/-0.249 LSB, an INL error of +0.275/-0.157 LSB, SNDR of 60.878 dB, SFDR of 72.9 dB and an ENOB of 9.82 bits. The average power consumption is 19.5 µW, resulting in a FoM of 4.31 fJ/conv-step.

論文審定書 i
中文摘要 ii
Abstract iii
Chapter1 緒論 1
1.1 研究動機與目標 1
1.2 論文主要架構 4
Chapter2 性能參數與基本架構說明 5
2.1 類比數位轉換器介紹 5
2.2 類比數位轉換器性能參數介紹 6
2.2.1 基本性能參數 6
2.2.2 靜態性能參數 8
2.2.3 動態性能參數 11
Chapter3 相關文獻介紹 14
3.1 連續漸進式類比數位轉換器介紹 14
3.2 電容陣列切換演算法介紹 16
3.2.1 傳統切換方式(Conventional Switching) 16
3.2.2 單調切換方式(Monotonic Switching) 17
3.2.3 基於共模切換方式(Vcm-based Switching) 19
3.2.4 平均充電切換方式(Charge Average Switching) 20
3.2.5 拆分合併切換方式(Merge and Split Switching) 21
3.2.6 單邊和高位元切換方式( One-side Switching Instead and Higher-bit Switching Instead) 22
3.2.7 輸入範圍自適應切換方式(Input-Range-Adaptive Switching) 24
3.2.8 猜測首兩位元切換方式(First 2-bit Guess Switching) 25
3.2.9 自適應重置切換方式(Adaptive-Reset Switching) 27
3.2.10 切換演算法總結 29
3.3 時域比較器介紹 30
3.3.1 基於Eye-opening VCO比較器 30
3.3.2 Edge-Pursuit比較器 32
3.3.3 應用於Adaptive Bypassing SAR ADC之基於VCO比較器 34
Chapter4 類比數位轉換器整體設計 36
4.1 連續漸進式類比數位轉換器之整體架構 36
4.2 連續漸進式類比數位轉換器運作流程 38
4.3 取樣保持電路 39
4.3.1 線性度(Linearity) 40
4.3.2 電荷注入(Charge Injection) 40
4.3.3 時序饋入(Clock Feedthrough) 41
4.3.4 兩階段拔靴帶式取樣保持電路 41
4.4 比較器 43
4.4.1 基於VCO之比較器 43
4.5 非同步控制邏輯 45
4.5.1 非同步控制邏輯架構 45
4.5.2 非同步控制邏輯運作波形 45
4.5.3 移位暫存器 46
4.6 電容陣列切換控制邏輯 47
4.6.1 自適應重置切換控制邏輯 47
4.6.2 CDAC切換控制邏輯 48
4.6.3 正緣觸發正反器 49
4.6.4 切換開關 49
4.7 電容陣列 50
Chapter5 模擬結果與佈局 52
5.1 取樣保持電路模擬與佈局 52
5.2 比較器模擬與佈局 54
5.3 全電路模擬與佈局 57
5.3.1 靜態分析 57
5.3.2 動態分析 59
5.3.3 功耗分佈 63
5.3.4 提出之SAR ADC佈局 64
5.4 效能比較 65
Chapter6 結論與未來展望 66
6.1 結論 66
6.2 未來展望 67
參考文獻 68

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