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研究生:陳維鴻
研究生(外文):Wei-Hong Chen
論文名稱:一個可適用於欠壓靜態隨機存取記憶體之兩階段離線測試與保護方法
論文名稱(外文):A Two-Stage Offline Test and Protection Method for Undervolted SRAM
指導教授:謝東佑
指導教授(外文):Hsieh,Tong-Yu
學位類別:碩士
校院名稱:國立中山大學
系所名稱:電機工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2024
畢業學年度:112
語文別:中文
論文頁數:86
中文關鍵詞:欠壓記憶體欠壓錯誤備援修復技術位元混淆技術出廠後測試
外文關鍵詞:undervolted memoryundervolting faultredundancy repair techniquebit-shuffling techniquein-field testing
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隨著多媒體應用在行動裝置上的蓬勃發展,對於算力門檻的提升連帶加劇了嵌入式靜態隨機存取記憶體的依賴程度,也帶來整體功耗的增加,嚴重影響電池的使用壽命。電壓調節技術(Voltage Scaling)是目前實現低功耗記憶體的主流方法,透過電壓與功耗間的平方關係,大幅降低SRAM的功耗。然而,隨著電壓下降,欠壓錯誤發生的機率呈指數級增長。使用傳統記憶體線下(off-line)修復技術會因為大量的欠壓錯誤導致修復成本顯著提升。過往文獻雖有基於欠壓錯誤開發線下保護技術,但並未將保護技術與線下測試流程進行結合,亦無討論出廠後測試(In-Field Testing)與保護的可能性。
因此,本論文基於欠壓記憶體開發線下兩階段測試與保護技術。分別使用位元混淆技術以及備援修復技術作為第一與第二階段保護方法。在第一階段測試中,我們使用單一測試序列⇕w1r1w0r0測試欠壓錯誤,並解決位元混淆保護方法中的混淆數值生成因測試成本無法於晶片上實現的問題。我們也開發混淆數值生成演算法,使用查找表(Look-Up Table)最小化在測試階段生成混淆數值需要花費的時間。最後,我們提出一個具成本效益之硬體架構,相較於窮舉實現方法,在減少2^16倍的排列組合數量下,平均僅增加2%的誤差。在第二階段中我們透過行進式測試演算法(March Testing)針對製程缺陷進行測試,並使用備援修復技術搭配非均勻保護概念,修復剩餘的高位元錯誤,達到更進一步的錯誤緩解。
與過往文獻進行保護效果和實現成本的比較,實驗結果指出在錯誤機率為10^(-3)時,相較於位元混淆技術,我們所開發的技術可以在提升1.6%的總面積成本下降低81%的MAE;相較於備援修復技術我們可以在下降5.1%的總面積成本下降低46%的MAE。我們也計算各自方法在所有可能配置下的實現成本和MAE的表現,進行柏拉圖最適性(Pareto Optimality)分析。實驗結果指出,在錯誤機率為10^(-3) 與10^(-2)下的柏拉圖最佳解前緣(Pareto frontier)中分別有83%與73%的數量是我們所開發的技術,說明本論文提出之方法在不同錯誤機率下,都能根據使用者對面積成本和MAE的限制提供更多配置選擇。
The surge in powerful mobile device usage has led to a significant increase in the need for multimedia applications on these devices. These complex applications require frequent access to embedded memory due to their intensive computational demands and heavy reliance on memory. Consequently, the substantial power consumption of embedded Static Random-Access Memories (SRAMs) restricts the battery life of mobile devices. Voltage scaling stands as the prevailing method to achieve low-power memory, substantially reducing SRAM power consumption by leveraging the square relationship between voltage and power. However, as voltage decreases, the probability of undervolting faults grows exponentially. Employing conventional offline memory repair techniques leads to a significant increase in repair costs due to a large number of undervolting faults. While past literature has developed offline protection techniques based on undervolting faults, they haven''t integrated these protective measures with offline testing processes nor discussed the feasibility of in-field testing and protection.
This thesis proposes a two-stage offline testing and protection technique based on undervolted SRAM memory. The proposed technique utilizes bit-shuffling and redundancy repair approaches as the first and second-stage protection methods. In the first-stage testing phase, a single test sequence ⇕w1r1w0r0 is employed targeting on undervolting faults, resolving the issue of generating shift values that cannot be feasibly implemented on-chip due to testing costs. Simultaneously, a shift value generation algorithm is developed, minimizing the time required to generate shift values during the testing phase using a Look-Up Table. Finally, a cost-effective hardware architecture is proposed that, compared to exhaustive approach, reduces an average of only 2% deviation while reducing permutations by a factor of 2^16. In the second stage, it employs the March testing algorithm to test manufacturing defects and uses redundancy repair techniques coupled with the concept of non-uniform protection to repair remaining high-bit errors, achieving further error mitigation.
Comparing the protective effects and implementation costs with past literature, our experimental results indicate that at an error rate of 10^(-3), compared to bit-shuffling, there is an 81% reduction in Mean Absolute Error (MAE) with a 1.6% increase in total area cost. Compared to redundancy repair techniques, there is a 46% reduction in MAE with a 5.1% decrease in total area cost. Finally, calculating the performance of each method in terms of implementation cost and MAE across all possible configurations, a Pareto Optimality analysis is conducted. The experimental results indicate that in the Pareto frontier of optimal solutions at error probabilities of 10^(-3) and 10^(-2), respectively, 83% and 73% of the solutions are attributed to our proposed technique, demonstrating that the proposed technique offers more configuration choices based on user constraints of area cost and MAE across different error probabilities.
論文審定書 i
致謝 ii
摘要 iv
Abstract vi
圖目錄 xi
表目錄 xiii
第一章 概論 1
1.1 論文背景與研究動機 1
1.2 論文章節摘要 4
第二章 研究背景與相關文獻 5
2.1 SRAM欠壓錯誤特性介紹 5
2.1.1 欠壓錯誤之穩定性 5
2.1.2 欠壓錯誤機率與電壓之關係 6
2.1.3 欠壓錯誤模型 7
2.2 記憶體備援修復技術 8
2.2.1 簡介 8
2.2.2 備援分析 9
2.3 基於欠壓記憶體開發之線下保護方法 12
2.3.1 位元混淆技術 — 基本架構 12
2.3.2 位元混淆技術 — 改良架構 14
第三章 兩階段測試與保護方法 16
3.1 既有文獻與方法之限制 16
3.1.1 傳統備援修復技術 16
3.1.2 位元混淆技術 16
3.2 提出之兩階段測試與保護架構 17
3.2.1 第一階段測試與保護架構 17
3.2.2 第二階段測試與保護架構 18
3.3 提出之兩階段測試流程以及硬體架構 19
第四章 混淆資訊生成技術 23
4.1 簡介 23
4.2 實驗流程設計 23
4.2.1 資料格式 23
4.2.2 誤差指標 23
4.2.3 錯誤注入 24
4.3 混淆資訊生成演算法之設計 25
4.3.1 簡介 25
4.3.2 Exhaustive Fault Map LUT 27
4.3.3 FM-LUT with Voter 28
4.3.4 Exhaustive Bit-Wise Sum LUT 31
4.3.5 Reduced Bit-Wise Sum LUT 33
4.3.6 Optimal Bit-Wise Sum LUT 36
4.4 硬體實現 38
4.4.1 簡介 38
4.4.1 位元累加單元 39
4.4.2 查找表 40
4.5 與多週期實現方法的比較 40
4.5.1 簡介 40
4.5.2 硬體實現架構 41
第五章 第二階段記憶體保護方法 44
5.1 簡介 44
5.2 第二階段保護方法 47
5.2.1 備援分析演算法—以MESP為例 47
5.2.2 MESP with 4-MSB範例 49
5.2.3 兩階段保護範例 52
5.3 兩階段保護之成效分析 53
5.3.1 實驗流程設計 54
5.3.2 實驗數據分析 55
第六章 硬體效能分析 58
6.1 簡介 58
6.2 實驗流程設計 58
6.3 實現成本評估方式 60
6.3.1 簡介 60
6.3.2 位元混淆技術 61
6.3.3 備援修復技術 61
6.3.4 兩階段保護技術 63
6.4 綜合效能分析 63
6.5 柏拉圖最適性分析 67
第七章 結論與未來展望 69
參考文獻 70
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