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研究生:吳明峻
研究生(外文):Ming-Jyun Wu
論文名稱:高效能三模式線性迴歸晶片之通用型硬體架構設計
論文名稱(外文):Unified Hardware Architecture of High-Performance Triple-Mode Linear Regression Chip
指導教授:施信毓
指導教授(外文):Shih,Xin-Yu
學位類別:碩士
校院名稱:國立中山大學
系所名稱:電機工程學系研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2024
畢業學年度:112
語文別:中文
論文頁數:80
中文關鍵詞:線性迴歸演算法硬體架構實現機器學習加速器多模式高效率訓練策略低延遲設計
外文關鍵詞:Linear RegressionHardware ImplementationMachine Learning AcceleratorMulti-modeHigh Efficiency Training StrategyLow-Latency Design
相關次數:
  • 被引用被引用:0
  • 點閱點閱:12
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隨著科技的不斷進步,人們的生活正日益受惠。近年來,人工智慧(AI)相關技術發展迅速,機器學習(Machine Learning)和深度學習(Deep Learning)已廣泛應用在不同的領域。常見的應用包括圖像辨識(Image Recognition)、語音辨識(Voice Recognition)、疾病偵測(Disease Detection)或是今日常見的自駕車系統之中。這些應用利用即時收集的大數據進行預測和分析。其中高效能晶片扮演著關鍵角色,提供了必要的運算能力。
隨著製程的不斷演進和第五代移動通訊技術(5G)的日益成熟,物聯網(Internet of Things, IoT)應用正迅速擴展。從穿戴式載具到智慧居家系統,再到衛生醫療和車聯網,各種相關應用正在改變我們的生活方式和工作模式。這些應用需要即時性的數據處理和分析,這就使得邊緣運算(Edge Computing)日益重視。因此,裝置上的機器學習晶片變得更加必要,以滿足對即時訓練和高速分類功能的需求。從而更好地支持終端設備的使用。這種整合機器學習模型到終端設備的趨勢,將更符合經濟效益。本論文提出高效能三模式線性迴歸晶片之通用型硬體架構設計,達到完整的硬體訓練暨分類解決方式。
本論文將提出三項技術,在保持模型準確率的狀況下同時提升線性迴歸演算法機器學習的訓練效率,(1)透過特徵與標籤之間的相關性,來判斷訓練資料的重要性,利用重要性差異,來達成訓練資料的篩選,減少訓練資料的總量,最終降低機器學習訓練的難度。(2)透過彈性選擇脊迴歸模型的參數,針對不同的訓練資料集進行訓練過程的調整,並透過硬體的設計,在不增加訓練難度的狀況下,得到最高準確度的機器學習模型。(3)透過降低特徵數量及群外點移除的功能,提出高效率的訓練策略,針對不一樣的訓練資料集進行調整,降低整體機器學習訓練難度,加速機器學習訓練。
Technological advancements have been continuously improving people''s lives. In recent years, AI-related technologies have developed rapidly, and machine learning and deep learning have been widely applied in various fields. Common applications include image recognition, voice recognition, disease detection, and self-driving car systems. These applications use real-time collected big data for prediction and analysis. High-performance chips play a key role in providing the necessary computing power.
With the advancement of technology and 5G, IoT applications are expanding rapidly. From wearables to smart homes to healthcare and connected cars, these applications are changing our lives and work. They require real-time data processing and analysis, which makes edge computing important. On-device machine learning chips are becoming necessary to meet the demand for real-time training and classification. This trend will be more cost-effective. This paper proposes a general-purpose hardware architecture design for a high-performance three-mode linear regression chip, which achieves a complete hardware training and classification solution.
This paper proposes three techniques to improve machine learning training efficiency. (1) Filter training data by judging its importance. (2) Adjust the training process for different datasets with parameter selection and hardware design. (3) Reduce the number of features and remove outliers to further reduce training difficulty. These techniques achieve a highly efficient machine learning training method.
論文審查書 i
誌謝 ii
摘要 iii
Abstract iv
圖次 vii
表次 ix
第1章 緒論 1
1.1背景 1
1.2動機與設計目標 2
1.3論文架構 4
第2章 線性迴歸介紹 5
2.1線性迴歸理論 5
2.2普通最小平方法線性迴歸演算法 6
2.3最小絕對值收斂和選擇算子線性迴歸演算法 7
2.4脊迴歸演算法 7
第3章 高效能三模式線性迴歸晶片之通用型硬體架構設計 9
3.1系統介紹 9
3.1.1軟硬整合式訓練及分類系統 9
3.1.2控制流程及外部參數介紹 14
3.1.3資料前處理及特徵資料集量化方式 15
3.2技術一:基於斯皮爾曼相關係數的機器學習資料前處理 20
3.2.1機器學習資料前處理降低樣本的重要性與原理 20
3.2.2 斯皮爾曼相關係數演算法介紹 21
3.2.3基於相關係數之機器學習資料前處理 23
3.2.4對多類機器學習模型準確度之分析 27
3.3技術二:自適應脊迴歸正則化參數選擇之設計 28
3.3.1 脊迴歸正則化參數重要性與原理 28
3.3.2正則化參數選擇之影響 30
3.3.3自適應正則化參數驗證設計 33
3.3.4準確度之分析 42
3.4技術三:高效率訓練加速策略 44
3.4.1群外點及低相關特徵移除之重要性 44
3.4.2基於資料統計之群外點移除器設計 45
3.4.3基於皮爾森積動差之低相關特徵排除器設計 49
3.4.4延遲與準確度分析 52
第4章 晶片實現 54
4.1標準元件晶片設計流程 54
4.2代碼覆蓋率 55
4.3合成結果分析 56
4.4可測試性晶片設計與分析 60
4.5晶片佈局成果 61
4.6效能比較 62
第5章 結語與未來展望 65
5.1結語 65
5.2未來展望 65
參考文獻 67
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