跳到主要內容

臺灣博碩士論文加值系統

(18.97.14.89) 您好!臺灣時間:2025/01/26 04:31
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:林嘉緯
研究生(外文):Lin, Chia-Wei
論文名稱:應用於三維積體電路再分佈層之基於沃羅諾伊圖多電源接地平面生成方法
論文名稱(外文):Voronoi Diagram-based Multiple Power/Ground Plane Generation on Redistribution Layers in 3D ICs
指導教授:林柏宏林柏宏引用關係
指導教授(外文):Lin, Po-Hung
口試委員:劉建男陳宏明
口試委員(外文):Liu, Chien-NanChen, Hung-Ming
口試日期:2024-01-02
學位類別:碩士
校院名稱:國立陽明交通大學
系所名稱:智慧系統與應用研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2024
畢業學年度:112
語文別:中文
論文頁數:43
中文關鍵詞:三維積體電路實體設計再分佈層電源接地平面沃羅諾伊圖
外文關鍵詞:3D-ICphysical designredistribution layer(RDL)power/ground planeVoronoi diagram
相關次數:
  • 被引用被引用:0
  • 點閱點閱:6
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
Acknowledgement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
摘要 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Related Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Our Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Overview of the Proposed Algorithms . . . . . . . . . . . . . . . . . . . . . . . . 7
4 Initial Power/Ground Plane Generation . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Disconnected Power Plane Violation . . . . . . . . . . . . . . . . . . . . . . . 12
5 Obstacle-aware Power/Ground Plane Legalization . . . . . . . . . . . . . . . . . 19
5.1 Floating Plane Reconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6 Cross-layer Power Integrity Enhancement . . . . . . . . . . . . . . . . . . . . . . 28
7 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
[1] K.-S. Hu, M.-J. Yang, Y.-H. Huang, B.-Y. Wong, and C. Shen, “ICCAD-2017 CAD contest in net open location finder with obstacles,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. IEEE Press, 2017, p. 863–866.
[2] H. Liao, V. Patil, X. Dong, D. Shanbhag, E. Fallon, T. Hogan, M. Spasojevic, and L. B. Kara, “Hierarchical automatic power plane generation with genetic optimization and multilayer perceptron,” arXiv:2210.16314 [cs.NE], 2022.
[3] C.-F. Tseng, C.-S. Liu, C.-H. Wu, and D. Yu, “InFO (wafer level integrated fan-out) technology,” in Proceedings of IEEE Electronics Components and Technology Conference, 2016, pp. 1–6.
[4] Y.-H. Lin, M. Yew, S. Chen, M. Liu, P. Kavle, T. Lai, C. Yu, F. Hsu, C. Chen, T. Fang, C. Hsu, K. Lee, C. Lin, P. Lin, and S.-P. Jeng, “Multilayer RDL interposer for heterogeneous device and module integration,” in Proceedings of IEEE Electronics Components and Technology Conference, 2019, pp. 931–936.
[5] H. Chen, C.-K. Cheng, A. Kahng, Q. Wang, and M. Mori, “Optimal planning for mesh-based power distribution,” in Proceedings of the Asia-South Pacific Design Automation Conference, 2004, pp. 444–449.
[6] S.-H. Wang, G.-H. Liou, Y.-Y. Su, and M. P.-H. Lin, “IR-aware power net routing for multi-voltage mixed-signal design,” in Proceedings of the Design, Automation & Test in Europe, 2019, pp. 72–77.
[7] M.-Y. Huang, H.-M. Chen, K.-N. Chen, S.-H. Wu, Y.-M. Lee, and A.-Y. Su, “A design flow for micro bump and stripe planning on modern chip-package co-design,” in Proceedings of IEEE Electronics Components and Technology Conference, 2020, pp. 2236–2241.
[8] D. Hyun, W. Lee, J. Park, and Y. Shin, “Integrated power distribution network synthesis for mixed macro blocks and standard cells,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 6, pp. 2211–2215, 2023.
[9] H.-T. Wen, Y.-J. Cai, Y. Hsu, and Y.-W. Chang, “Via-based redistribution layer routing for InFO packages with irregular pad structures,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 12, pp. 5554–5567, 2022.
[10] Y.-T. Chen and Y.-W. Chang, “Obstacle-avoiding multiple redistribution layer routing with irregular structures,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2022, pp. 1–6.
[11] Y.-H. Chang, H.-T. Wen, and Y.-W. Chang, “Obstacle-aware group-based length-matching routing for pre-assignment area-I/O flip-chip designs,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2019, pp. 1–8.
[12] Y.-K. Ho, H.-C. Lee, W. Lee, Y.-W. Chang, C.-F. Chang, I.-J. Lin, and C.-F. Shen, “Obstacle-avoiding free-assignment routing for flip-chip designs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 2, pp. 224–236, 2014.
[13] R. Bairamkulov, A. Roy, M. Nagarajan, V. Srinivas, and E. G. Friedman, “SPROUT—Smart power routing tool for board-level exploration and prototyping,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 7, pp. 2263–2275, 2022.
[14] S. Fortune, “A sweepline algorithm for Voronoi diagrams,” in Proceedings of the 2nd Annual Symposium on Computational Geometry, 1986, p. 313–322.
[15] G.-Q. Fang, Y. Zhong, Y.-H. Cheng, and S.-Y. Fang, “Obstacle-avoiding open-net connector with precise shortest distance estimation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 5, pp. 1096–1108, 2020.
[16] Y.-Y. Su, S.-H. Wang, W.-L. Wu, and M. P.-H. Lin, “Corner-stitching-based multilayer obstacle-avoiding component-to-component rectilinear minimum spanning tree construction,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 3, pp. 675–685, 2020.
[17] B.-H. Jiang and H.-M. Chen, “Extending ML-OARSMT to net open locator with efficient and effective boolean operations,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2018, pp. 1–8.
[18] R.-Y. Wang, C.-C. Pai, J.-J. Wang, H.-T. Wen, Y.-C. Pai, Y.-W. Chang, J. C.M. Li, and J.-H. Jiang, “Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction,” in Proceedings of the ACM/IEEE Design Automation Conference, 2018, pp. 1–6.
連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top