臺灣博碩士論文加值系統

隨著物聯網技術的進步以及普及，有著多樣化的應用及產品，因應而來的需求便是無線及有線傳輸，因此晶片內的收發器便扮演著不可或缺的角色。在大多數的收發系統內，頻率合成器提供訊號的參考頻率。本篇論文中將針對上述之議題提出無線及有線架構的核心電路設計。
第一個部分是雙導通Class-C壓控震盪器(VCO)，使用台積電0.18微米Mixed Single/RF製程實現。這個振盪器架構透過雙導通架構降低雜訊，並將MOS的源端加上衰減電容，使得電路能夠減少元件的寄生電容，從而實現高頻應用。量測結果顯示，在VDD=1.2V時，振盪頻率為10 GHz，在1 MHz處的相位雜訊為-93.5 dBc/Hz，總直流功耗為4.4 mW。
第二部分為10 GHz低雜訊次取樣鎖相迴路(SSPLL)，同樣使用台積電0.18微米Mixed Single/RF製程製作。該架構採用單一電流泵設計。為了實現低雜訊，整體的功耗為15.2 mW。參考頻率為40 MHz，輸出頻率對參考頻率的功率比為-37.4 dBc，相位雜訊在1 MHz 的偏移處為-108 dBc/Hz，在 10 MHz 的偏移處的相位雜訊為-120 dBc/Hz。

With the advancement and proliferation of IoT technology, a diverse array of applications and products have emerged, leading to increased demand for both wireless and wired transmission. Transceivers within chips thus play an indispensable role in meeting these demands. In most transceiver systems, frequency synthesizers provide the reference frequency for the signal. This thesis addresses the core circuit design for wireless and wired architectures in response to the aforementioned issues.
The first part discusses a dual-conduction Class-C voltage-controlled oscillator (VCO), implemented using TSMC 0.18 μm Mixed Single/RF process. This oscillator architecture reduces noise through a dual-conduction design and incorporates attenuation capacitors at the source of the MOS transistors to reduce parasitic capacitance, enabling high-frequency applications. Measurement results show that at VDD=1.2V, the oscillation frequency is 10 GHz, the phase noise at 1 MHz is -93.5 dBc/Hz, and the total DC power consumption is 4.4 mW.
The second part focuses on a 10 GHz low-noise subsampling phase-locked loop (SSPLL), also fabricated using TSMC 0.18 μm Mixed Single/RF process. This architecture employs a single charge pump design. To achieve low noise, the total power consumption is 15.2 mW. With a reference frequency of 40 MHz, the power ratio of the output frequency to the reference frequency is -37.4 dBc. The phase noise is -108 dBc/Hz at a 1 MHz offset and -120 dBc/Hz at a 10 MHz offset.

摘要 i
ABSTRACT ii
目錄 v
表目錄 viii
圖目錄 ix
第一章 緒論 1
1.1 研究背景與動機 1
第二章 低功耗雙導通Class-C VCO 2
2.1 振盪器效能參數簡介 2
2.1.1 相位雜訊 2
2.1.2 相位雜訊對系統的影響 3
2.1.3 相位雜訊在時域的關係 3
2.1.4 調頻範圍與輸出功率 4
2.1.5 負載效應 5
2.2 基本振盪器 6
2.3 電路架構 6
2.4 電路設計與實現 8
2.5 模擬與量測 14
2.5.1 量測結果 16
2.5.2 結果討論 21
第三章 鎖相迴路與次取樣技術概論 22
3.1 Type-I鎖相迴路 22
3.2 電流泵鎖相迴路 23
3.2.1 相位頻率檢測器及電流泵 24
3.2.2 迴路濾波器 26
3.2.3 除頻器 28
3.3 鎖相迴路的線性模型 29
3.3.1 相位頻率檢測器和電流泵的線性模型 29
3.3.2 低通濾波器的線性模型 30
3.3.3 壓控振盪器的線性模型 30
3.3.4 鎖相迴路的穩定性分析 30
3.4 次取樣鎖相迴路 32
3.4.1 頻率鎖定迴路的操作 33
3.4.2 核心迴路的操作 33
3.4.3 次取樣鎖相迴路和電流泵鎖相迴路的雜訊分析比較 34
3.5 鎖相迴路的設計流程 35
第四章 次取樣鎖相迴路硬體設計與實現 36
4.1 本論文次取樣鎖相迴路架構 36
4.2 各個子電路架構 36
4.2.1 頻率檢測器與死區產生 36
4.2.2 脈衝產生器 37
4.2.3 次取樣相位偵測器 38
4.2.4 電流泵 39
4.2.5 壓控振盪器 42
4.2.6 輸出級 43
4.2.7 訊號時序 44
4.3 迴路系統及雜訊分析 46
4.4 電路特性模擬 48
4.4.1 雜訊分析 49
第五章 結論與未來展望 54
5.1 結論 54
5.2 未來展望 54
參考文獻 55

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