臺灣博碩士論文加值系統

本文設計了一個符合MIPI A-PHY規範的非對稱同步雙向收發器。在MIPI A-PHY
的規範中，非對稱同步雙向收發器僅使用一條通道來傳輸資料，而通道兩端都各有
一個傳送機和接收器，因此來自通道兩側的傳送機信號以及由通道產生的信號反
射會同時被接收器接收。上述兩個問題會導致接收器無法接收到正確的資料並還
原，所以使用了一種具寬線性範圍且帶有調整迴轉率功能的混合電路，以分離兩個
傳送機的信號，確保接收機不會被同一側傳送機的訊號干擾，並採用回波消除器來
去除通道反射。
此外，A-PHY推出的主旨也在於解決長距離數據傳輸的問題。像是車用的系統
中，兩端資料傳輸通常會使用較長的通道，這可能會有嚴重的通道損耗及干擾導致
訊號失真等問題，所以本文使用了前端電路以補償長距離傳輸中的通道損耗，並調
節訊號增益。也使用三標記決策回饋等化器來消除前端電路沒有完全消除的通道
損耗，在調整時鐘訊號相位的部分加入時脈資料恢復電路來確保時鐘訊號取樣的
穩定和準確性，使整個系統更完整。最終，在28-nm CMOS製程下，實現一個符合
MIPI A-PHY規範的 8-Gb/s 四階脈衝振幅調變非對稱同步雙向接收器，以及一個
100-Mb/s 不歸零發射器，以滿足當前MIPI A-PHY對於資料傳輸需求。
量測時類比前端電路的VDD使用1.2V，其餘電路使用0.9V。量測結果也有達到
A-PHY規定的速度8Gb/s和4Gb/s 。

This thesis presents the design of an asymmetric simultaneous bidirectional
transceiver that complies with the MIPI A-PHY standard. According to the MIPI A-PHYspecification, the asymmetric simultaneous bidirectional transceiver uses a single channel for data transmission, with a transmitter and receiver at each end of the channel. As a result, the receiver simultaneously receives signals from both transmitters and reflections caused by the channel. These issues can lead to the receiver being unable to correctly receive and reconstruct the data. To address these problems, we implemented a hybrid circuit with a wide linear range and adjustable slew rate to separate the signals from the two transmitters, ensuring that the receiver is not affected by the signal from the
transmitter on the same side. Additionally, an echo canceller is employed to eliminate channel reflections.
Moreover, the primary goal of A-PHY is to tackle the challenges of long-distance
data transmission. In automotive systems, for example, data transmission often occurs over long channels, which can result in significant channel loss and interference, leading to signal distortion. To mitigate these problems, this thesis uses a front-end circuit to compensate for channel loss over long-distance transmission and to adjust signal gain. A three-tap decision feedback equalizer is also used to eliminate residual channel loss that the front-end circuit does not fully address. Clock and data recovery circuits are incorporated to ensure the stability and accuracy of clock signal sampling, thereby enhancing the overall system integrity. Finally, a 28-nm CMOS process was used to implement an 8-Gb/s four-level pulse amplitude modulation (PAM-4) asymmetric simultaneous bidirectional receiver and a 100-Mb/s non-return-to-zero (NRZ) transmitter that comply with the MIPI A-PHY standard to meet current data transmission requirements.
During measurement, the analog front-end circuit used a VDD of 1.2 volts, while
the remaining circuits used 0.9 volts. The measurement results also achieved the speeds specified by the A-PHY standard, reaching 8Gb/s and 4Gb/s.

Contents
摘要...................................................................................................................................ii
Abstract...........................................................................................................................iii
誌謝...................................................................................................................................v
Contents ..........................................................................................................................vi
List of Figures...............................................................................................................viii
List of Tables .................................................................................................................xii
Chapter1 Introduction.............................................................................................1
1.1 Motivation........................................................................................................1
1.2 Recent Research ..............................................................................................6
Chapter2 Basic Theory ..........................................................................................11
2.1 Bidirectional Receiver Architecture............................................................11
2.2 Hybrid Circuit...............................................................................................12
2.3 Continuous Time Linear Equalizer.............................................................13
2.4 Decision Feedback Equalizer .......................................................................14
2.5 Clock and Data Recovery (CDR).................................................................15
2.5.1 Bang-Bang Phase Detector (BBPD).........................................................15
2.5.2 Digital Loop Filter.....................................................................................17
2.5.3 Phase Interpolator.....................................................................................18
Chapter3 Design of the Asymmetric Simultaneous Bidirectional Transceivers ..
.................................................................................................................18
3.1 Overview ........................................................................................................19
3.2 Uplink & WLR Hybrid Building Block ......................................................21
3.3 Analog Front-End .........................................................................................26
3.3.1 CTLE..........................................................................................................27
3.3.2 VGA............................................................................................................31
3.3.3 Echo Cancel ...............................................................................................36
vii
3.4 Decision Feedback Equalizer .......................................................................43
3.5 Clock path......................................................................................................48
3.5.1 IQ divider...................................................................................................49
3.5.2 Phase Interpolator.....................................................................................50
3.5.3 Uplink Clock Path.....................................................................................53
Chapter4 Measurement .........................................................................................56
4.1 Measurement SetUp......................................................................................56
4.2 Experimental Results....................................................................................57
Chapter5 Conclusion and Future work ...............................................................63
5.1 Conclusion......................................................................................................63
5.2 Future work ...................................................................................................64
Chapter6 Reference................................................................................................65

Chapter6 Reference
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