臺灣博碩士論文加值系統

本論文旨在設計一個可以供多功能數位碟片讀取裝置使用的感光二極體與轉阻放大器電路，這篇論文裡有分別使用兩個製程製作這個晶片，一個是使用一標準點60微米2P2M 補式金氧半導體製程製作，另一個是使用一標準點35微米1P4M 補式金氧半導體製程製作。這個電路是讀取由多功能數位碟片反射的雷射光信號，雷射光信號用感光二極體接收並感應出電流，電流信號由轉阻放大器放大並轉成電壓輸出。此轉阻放大器在加上了一個新的補償電路後，順利的將-3dB頻寬推到129 MHz和164 MHz，大於現今一般的多功能數位碟片讀取裝置所要求的24 MHz。現在的多功能數位碟片讀取裝置裡面的雷射光是使用波段為650 nm的雷射光，在標準的補式金氧半導體製程可以製作的感光二極體中，最符合這個電路要求的感光二極體是n-well/p-substrate感光二極體，當此感光二極體的面積為250 um×200 um時，每瓦特的雷射可以感應出0.065安培的電流。用標準點60微米2P2M 補式金氧半導體製程製作的晶片在電壓為5 V時，耗損的功率為62 mW。

A photodiode and transimpedance amplifier circuit is presented in this thesis. This circuit has been fabricated by two processes. These two processes are 0.60 μm double-poly-double-metal (2P2M) CMOS process and 0.35 μm single-poly-four-level-metal (1P4M) CMOS process. The laser light reflected from the disk is read into photodiode and transimpedance amplifier circuit. The light signal is sensed by photodiode and then turned into photocurrent. The photocurrent is transformed to the voltage signal by the transimpedance amplifier. The -3dB frequency of this transimpedance amplifier with the new compensation circuit is designed to 160 MHz. In CMOS process, the most suitable photodiode which is sensitive to the red laser with wavelength of 650 nm used in the DVD player is n-well/p-substrate photodiode. The sensitivity of n-well/p-sub photodiode is 1.3*10E-7 A/W•um2. The power dissipation of the proposed chip fabricated by standard 0.60 μm double-poly-doule-metal CMOS process is 62 mW under 5 V power supply voltage.

Chapter 1 INTRODUCTION
1.1. BACKGROUND
1.2. MOTIVATION
1.3. ORGANIZATION OF THIS THESIS 3
Chapter 2 THE DESIGN OF LOW— LEAKAGE — CURRENT AND HIGH — PHOTO — SENSITIVITY CMOS PHOTODIODE
2.1. THE CHARACTERISTICS OF CMOS PHOTODIODE
2.2. The STRUCTURES OF CMOS PHOTODIODE
2.2.1. n+ / p-well Photodiode
2.2.2. n-well / p+ Photodiode
2.2.3. n-well / p-substrate Photodiode
2.3. EXPEREMENTAL RESULTS AND PERFORMANCE ANALYSIS OF CMOS PHOTODIODE
Chapter 3 THE DESIGN OF TRANSIMPEDANCE AMPLIFIER
3.1. HIGH-SPEED TRANSIMPEDANCE AMPLIFIER
3.2. SIMULATION RESULTS 29
3.2.1. Bandwidth of 100 MHz OEIC in Chaptered 0.6 m 2P2M CMOS Process
3.2.2. Bandwidth of 160 MHz OEIC in TSMC 0.35 m 1P4M CMOS Process
Chapter 4 LAYOUT DESCRIPTIONS AND
EXPERIMENTAL RESULTS OF OEIC
4.1 LAYOUT DESCRIPTIONS
4.2 TESTINFG SYSTEM SETUP
4.3 EXPERIMENTAL RESULTS
Chapter 5 CONCLUSIONS AND FUTURE WORKS
52
5.1 CONCLUSIONS
5.2 FUTURE WORKS

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