臺灣博碩士論文加值系統

由於網際網路的快速成長，急速增加的資料傳輸造成光纖通訊對於大量傳輸能力的需求增加。為了符合這樣的需求，操作在百億位元傳輸速率的光纖通訊收發機設計已發表在數篇論文中。光纖通訊收發機的操作速率主要受限於它的光電介面：傳送端的Lasers與接收端的Photodiodes。因此，光纖通訊積體電路系統中的速度瓶頸便是接收端的前端放大器，包含轉阻放大器(Transimpedance amplifier)與限制放大器(Limiting amplifier)，與傳送端的雷射驅動電路(Laser driver)。
本篇論文中的百億位元轉阻放大器是利用0.18-μm CMOS製程實現。為了改善此電路的overload效應，此放大器包含了一個自動增益控制機制。此迴路設計是由平均電壓偵測器、比較器、電壓電流轉換器與一個外接的迴路濾波器構成。為了在電路設計的階段能夠正確預測自動增益控制的效能，本篇論文對此迴路的特性有詳細的數學分析。實驗結果顯示，以一個2.0伏特的電壓供應60毫瓦的功率下，本次設計的轉阻放大器能夠達到45 dBΩ的轉阻增益與8.6 GHz的小訊號頻寬。自動增益控制的測試結果顯示，在百億位元、231-1 PRBS的輸入訊號下，此電路在-21 dBm到1 dBm的輸入訊號強度之間都能夠符合小於10-12的誤碼率。
在本論文中提出了一種電路技巧能夠在不使用被動電感的情況下實現一個百億位元的限制放大器。使用三階的交錯式主動回授架構能夠有效的增加放大器頻寬並壓抑gain peaking。以0.18-μm CMOS製程實現，在供應電壓1.8伏特、消耗功率189毫瓦的情況下，此電路能夠提供42 dB的電壓增益與9.0 GHz的小訊號頻寬。在百億位元、231-1 PRBS的輸入訊號下，此放大器能夠輸出電壓振幅大於300 mV，而在輸入訊號強度大於10 mV的情況下，此電路都能夠符合小於10-12的誤碼率。由於本次設計不需使用電感，晶片面積僅有0.68x0.8 mm2，而主動電路的部分僅佔0.32x0.6 mm2。

As a result of the enormous growth of internet and intranet, the rapid increase of data traffic leads to a vast demand of huge capacity of optical communication systems. In recently published papers, optical transmission systems operating at 10 Gb/s have been developed to fulfill such demand. Data rates in optical communication systems are mainly limited by their electrical interfaces with the available optoelectronic devices such as the lasers in transmission end and the photo-diode in the front-end of the receiver. Therefore, the most speed critical integrated circuits (ICs) in the systems are the analog front-end including transimpedance amplifier and limiting amplifier in the receiver and the laser driver in the transmitter.
The 10-Gb/s transimpedance amplifier (TIA) presented in this thesis is implemented in a standard 0.18-μm CMOS technology. In order to improve the overload characteristic, the automatic gain control (AGC) composed of the average detector, the comparator and the voltage-current converter followed by the off-chip loop filter is included in this work. The detail analysis of the AGC behavior model including linear and bang-bang operation is presented to predict the performance of the gain control mechanism. The experimental results show the TIA achieves a transimpedance gain of 45 dBΩ and a -3-dB bandwidth over 8.6 GHz with 60-mW power dissipation from a 2.0-V supply. Along with the AGC circuit, the fabricated circuit that is tested in 10-Gb/s, 231-1 PRBS exhibits a sensitivity of -21 dBm and an overload threshold of 1 dBm.
An inductorless circuit technique is presented for CMOS limiting amplifiers. By employing the third-order interleaving active feedback, the bandwidth of the proposed circuit can be effectively enhanced while maintaining a suppressed gain peaking within the frequency band. Using a standard 0.18-um CMOS process, the limiting amplifier is implemented for 10-Gb/s broadband applications. Consuming a dc power of 189 mW from a 1.8-V supply voltage, the fabricated circuit exhibits a voltage gain of 42 dB and a -3-dB bandwidth of 9 GHz. With a 231-1 pseudo-random bit sequence at 10 Gb/s, the measured output swing and input sensitivity for a bit-error-rate of 10-12 are 300 and 10 mVpp, respectively. Due to the absence of the spiral inductors, the chip size of the limiting amplifier including the pads is 0.68x0.8 mm2 where the active circuit area only occupies 0.32x0.6 mm2.

Chapter1 Introduction 1
1.1 Motivation 1
1.2 Overview of the thesis 2

Chapter2 Basic Concepts of Optical Receiver Analog Front-end Circuits 4
2.1 Background of Optical Communication Systems 4
2.2 Basic Concepts 7
2.2.1 Basic Concepts of Photodetector 7
2.2.2 Basic Concepts of Preamplifier 8
2.2.3 Basic Concepts of Post-amplifier 10

Chapter 3 A 10-Gb/s CMOS Transimpedance Amplifier with Automatic Gain Control 15
3.1 Introduction 15
3.2 Analysis of Automatic-Gain-Control Loop 16
3.2.1 Behavior Model of AGC Loop 17
3.2.2 Closed-loop Response to Iin 18
3.2.3 Closed-loop Response to Vref 26
3.3 Circuit Design 29
3.3.1 Variable-gain Amplifier 29
3.3.2 Average Detector 32
3.3.3 Comparator 32
3.3.4 Voltage-current Converter 33
3.3.5 Closed-loop Simulation 34
3.4 Experimental Results 35
3.5 Conclusion 39

Chapter 4 A 10-Gb/s Inductorless CMOS Limiting Amplifier with Third-order Interleaving Active Feedback 42
4.1 Introduction 42
4.2 Limiting Amplifier Architecture 43
4.2.1 General Consideration of Cascaded Gain Stages 43
4.2.2 Analysis of Third-order Gain Stages with Active Feedback 46
4.3 Proposed Interleaving Feedback Topology 49
4.3.1 Bandwidth Enhancement 50
4.3.2 Reduction of Gain peaking and Overshoot 52
4.4 Circuit Design 56
4.4.1 Amplifier Core 56
4.4.2 Offset Cancellation 60
4.4.3 Output Buffer 61
4.5 Experimental Results and Discussion 62
4.5.1 Measurement Setup and Experimental Results 62
4.5.2 Discussion 66
4.6 Conclusion 67

Chapter 5 Conclusion 69

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