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研究生:黃鴻運
研究生(外文):Hung-Yun Huang
論文名稱:架構於低傳輸交換之低功率晶片網路架構
論文名稱(外文):A Low power Network-on-Chip Architecture Based on Low Switching Method
指導教授:賴飛羆賴飛羆引用關係
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電機工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2007
畢業學年度:95
語文別:英文
論文頁數:49
中文關鍵詞:晶片網路低功率晶片系統網路介面匯流排反向
外文關鍵詞:Network-on-ChipLow powerSystem-on-ChipNetwork InterfaceBus-invert
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低功率超大型積體電路設計是目前最重要的一個議題之一,在晶片系統(System-on-Chip)中,隨著日漸複雜的設計以及IP數目的不斷增加,各IP之間的資料傳遞上成為了一大挑戰,為解決資料傳遞上所產生的問題,目前有許多研究提出以晶片網路(Network-on-Chip)的方式來解決IP之間的資料傳輸問題。在晶片網路架構中,其主要元件為:交換器(Switch)及網路介面(Network Interface, NI)。在本篇論文中,我們提出一個運用在二維網路拓撲(2-D Mesh Topology)上之低傳輸交換編碼的網路介面(Low-Switching Network Interface, LSNI)利用匯流排反向之技術對傳輸資料重新編碼來達到低功率之目的。根據本篇論文實驗結果,當資料傳輸功率占全部功率的80%時,使用本篇所提之方法,平均可節省之功率消耗約20%。本篇研究可有效的減少資料傳輸的交換次數來節省晶片網路的功率消耗。
The design of the Low power VLSI circuit is one of the most important issues at the present time technology. In the SoC (System-on-Chip), with ever increasing complexity of VLSI design and IP cores, the inter-communication between IP cores becomes the noteworthy challenge. In order to solve the problem of the data communication, the Network-on-Chip is proposed to deal with the difficulties of inter-communication between IP cores. In the NoC, the main components are Switch (or so-called Router) and Network Interface (NI, or so-called Wrapper). In this thesis, we propose a low-switching network interface used in the 2D mesh topology and the bus-invert method, we can accomplish the goal of the low power for recoding the data. According to the experimental results, with the method mentioned in this thesis, the power consumption can be saved about 20% on average when the percentage of the inter-connection power in the total power is 80%. In this work, we can effectively reduce the switching activity of the data transfer to save the power consumption of the NoC data-communication.
1 Introduction 1
1.1 The purpose of low power 1
1.2 Power dissipation in CMOS VLSI circuit 2
1.2.1 Dynamic power dissipation 2
1.2.2 Static power dissipation 3
1.3 The concept of the NoC(Network-on-Chip) 4
1.4 Thesis organization 6

2 Related Work 7
2.1 Network protocol of the NoC 7
2.2 NoCs topology 10
2.2.1 Mesh type topologies 10
2.2.2 Tree type topologies 12
2.2.3 Ring type topologies 14
2.3 Routing algorithm 15
2.3.1 XY-routing algorithm 15
2.3.2 DyXY routing algorithm 16
2.3.3 Odd-even turn model 18
2.3.4 West-first routing algorithm 18
2.4 Switching methods 20
2.5 Network Interface 23

3 Proposed Low Power Network-on-Chip Architecture 24
3.1 The motivation and the basic design concept 24
3.2 Proposed Network Interface architecture 24
3.2.1 Bus-invert method 25
3.2.2 The critical problem of previous research 27
3.2.3 Low switching network interface architecture(LSNI) 28
3.3 Packet format 32
3.4 Deadlock problem and our switch architecture 33

4 Experimental Results 38
4.1 Experimental environment 38
4.2 Experimental results 41

5 Conclusion 46

Reference
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[2] L. Benini and G. D. Micheli, “Networks on Chip: A New SoC paradigm,” IEEE Computer, vol. 35, no. 1, pp.78-80, Jan. 2002.

[3] P. P. Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh, “Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures,” IEEE Trans on Computer, vol. 54, no. 8, pp.1025-1040, Auq. 2005.

[4] D. Bertozzi and L. Benini, “Xpipes: A Network-on-Chip Architecture for Gigascale Systems-on-Chip,” IEEE Circuit and Systems Magazine, vol. 4, no. 2, pp.18-31, 2004.

[5] K. C. Saraswat et al., “Technology and Reliability Constrained Future Copper Interconnects – Part II: Performance Implications,” IEEE Trans. On Electron Device, vol. 49, no. 4, pp.598-640, Apr. 2002.

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[8] P. P. Pande, C. Grecu, A. Ivanov, and R. Saleh, “Design of a Switch for Network on Chip Applications, ” in IEEE Proc. Int’l Symp. On Circuits and Systems (ISCAS), pp.217-220, May, 2003.

[9] F. Karim et al., “An Interconnect Architecture for Networking Systems on Chips,” IEEE Micro, vol. 22, no. 5, pp.36-45, Sept. /Oct. 2002.

[10] Ming Li, Qing-An Zeng, Wen-Ben Jone, “DyXY-A Proximity Congestion-Aware Deadlock-Free Dynamic Routing Method for Network on Chip,” in IEEE/ACM Proc. Of Design Automation Conference (DAC), pp.24-28, July, 2006.

[11] G. M. Chiu, “The Odd-Even Turn Model for Adaptive Routing,” IEEE Transaction on parallel and Distributed Systems, vol. 11, issue 7, pp.729-738, July, 2000.

[12] C. A. Zeferino, M. E. Kreutz, A. A. Suisn, “RASoC: a router soft-core for networks-on-chip,” in Proc. of Design, Automation and Test in Europe Conference and Exhibition, vol. 3, pp.198-203, Feb, 2004.

[13] C. A. Zeferino, A. A. Suisn, “SoCIN: a parametric and scalable network-on-chip,” in Proc. of Symposium on Integrated Circuits and System Design, vol. 3, pp.169-174, Sept, 2003.

[14] C. A. Zeferino, F. G. M. E. Santo, A. A. Suisn, “ParIS: a paramaterizable interconnect switch for network-on-chip,” in Proc. of Symposium on Integrated Circuits and System Design, pp. 204-209, Sept, 2004.

[15] P. T. Wolkotte, G. J. M. Smit, G. K. Rauwerda, L. T. Smit, “An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip,” in Proc. of IEEE International Parallel and Distributed Processing Symposium, pp.155a-155a, April, 2005.

[16] Daewook Kim, Manho Kim, G. E. Sobelman,” NIUGAP: low latency network interface architecture with Gray code for networks-on-chip,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), May, 2006.

[17] Praveen Bhojwani and Rabi N. Mahapatra,” Core network interface architecture and latency constrained on-chip communication,” in Proc. of IEEE International Symposium on Quality Electronic Design (ISQED), March, 2006.

[18] Chia-Ming Wu, Hsin-Chou Chi, Ying-Ming Huang,” A Wrapper for Low-Power Error-Correcting Data Delivery in On-Chip Networks” in Proc.Of IEEE International Conference on Communications, Circuits and Systems Proceedings(ICCCAS), vol. 4, pp.2662-2666, June, 2006.

[19] M.R. Stan, and W.P. Burleson, “Bus-Invert Coding for Low-Power I/0,” IEEE Trans. VLSI Systems, vol. 3, Issue 1, pp.49-58, March 1995.

[20] H. Wang, L. Peh, and S. Malik, “Power-driven design of router microarchitectures in on-chip networks,” In Proc. the 36th International Conference on Microarchitecture, Dec. 2003.

[21] I. Corporation. A touchstone delta system description. In Intel Advanced Information, 1991.

[22] C. J. Glass and L. M. Ni, “The turn model for adaptive routing,” Proceedings of the 19th International Symposium on Computer Architecture, pp. 278–287, May 1992.
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