移動物件偵測在視訊監控是非常重要的一個研究課題。現今雖然已有許多方法可以偵測移動物件，但皆以個人電腦來實現，因此會具有效率低與功耗大之缺點。本論文提出使用硬體電路來直接進行移動物件偵測，在RTL層級以Verilog HDL來設計，並於FPGA實現。所提出的RTBS(Real-time Background Subtraction)方法是將背景相減演算法改良，達到可以不用除法器與跟號運算以進行背景更新、背景相減與動態閥值等目的。根據該RTBS演算法而提出的硬體架構，則以功能切割與任務切割方法，將背景相減切割成平行化的功能與任務，並設計7 階段之管線架構，之後也使用硬體設計分別加入型態學法(Morphology)的Opening與Closing方法將背景相減的影像作雜訊消除與區塊修補之效。本研究於影像解析度在VGA(640X480)時，使用模擬來分析FPGA即時物件偵測硬體處理部份，其最高處理效能可達到368fps，而模擬整體發展系統處理效能為56fps，而實際的實驗驗證可達到51fps。整個也系統僅使用2個Frame Buffer來處理。

Moving object detection is a very important research topic for video surveillance. Although there are many proposed methods to detect moving object, but most of these methods are implemented on personal computer. Therefore, drawbacks of low computational efficiency and high power consumption are very critical to this systems. This paper proposes hardware architecture for moving object detection, which is designed using Verilog HDL, and implemented on FPGA. We propose an algorithm of RTBS(Real-time Background Subtraction), it is improvement and base on background subtraction algorithm. The method hasn't to use any operation of division and radical which implement background update, background subtraction and adaptive threshold. Function partition and task partition are analyzed to improve the performance throughput and area consumption which base on RTBS algorithm. The seven-stage pipeline with three-clock latency is designed to improve the parallelism of the system. After background subtraction is using morphology method, the method is used to filter noise (Opening) and to reconnect split object (Closing). In our simulation, throughput of 368 fps can be achieved for the background subtraction module processing real-time videos with VGA(640x480) resolution. 56 fps can be achieved in simulation for the whole system, which includes camera data acquisition, memory control, and other four modules. In system verification, throughput of 51 fps is verified. The results validate the high efficiency of the proposed architecture design. The system only uses 2 frame buffers for implementation.

中文摘要 i
英文摘要 ii
誌謝 iii
目錄 iv
表目錄 vi
圖目錄 vii
第1章 前言 1
1.1 研究背景與動機 1
1.2 研究目的 3
1.3 移動物件偵測文獻探討 3
1.4 硬體架構探討 6
1.5 系統架構 9
1.6 論文架構 12
第2章 管線、功能與資料分割架構 14
2.1 管線分割 14
2.2 功能分割 18
2.3 資料分割 20
第3章 背景相減硬體架構 22
3.1背景相減演算法 22
3.2 BS演算法之改良 27
3.3 RTBS背景相減法之硬體架構設計 30
第4章 型態學法硬體架構 39
4.1型態學法 40
4.2型態學法之硬體架構設計 44
第5章 模擬分析與驗證 49
5.1 視訊實驗之驗證 49
5.2 Frame Rate分析 54
5.3 BS演算法與RTBS演算法之差異比較 59
5.4 FPGA硬體資源使用狀況 60
第6章 結論 62
參考文獻 64
附錄A. 輸出入硬體模組說明 67
A.1 RAW Data轉換RGB值 67
A.2 影像映射(Mirror) 71
A.3 影像灰階(Gray Level)轉換 72
A.4 SDRAM 控制器 76
附錄B. 本系統之開發環境 79
B.1 DE2硬體架構 81
B.2 CYCLONE-II場效可程式化邏輯陣列(FPGA) 83
B.3 130萬像素CMOS Sensor 模組 85
B.4 QUARTUS-II發展工具系統 87
附錄C. 重要模組之Net List 90
C.1 Background Subtraction and Update區塊RTL的Net-list 90
C.2 Morphology區塊RTL的Net-list 91

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