跳到主要內容

臺灣博碩士論文加值系統

(18.97.14.86) 您好!臺灣時間:2025/02/08 02:10
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:孫詩佳
研究生(外文):Shi-Jia Sun
論文名稱:1至16倍速DVD燒錄器寫入時脈訊號產生器
論文名稱(外文):A Clock Generator for 1X~16X DVD Recorder Write Pulse
指導教授:黃弘一
指導教授(外文):Hong-Yi Huang
口試委員:鄭國興劉榮宜劉萬榮洪浩喬
學位類別:碩士
校院名稱:國立臺北大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:中文
論文頁數:63
中文關鍵詞:電壓控制震盪器全數位式鎖頻迴路數位類比轉換器連續近似暫存器控制
外文關鍵詞:VCOADFLLD/ASAR
相關次數:
  • 被引用被引用:0
  • 點閱點閱:268
  • 評分評分:
  • 下載下載:35
  • 收藏至我的研究室書目清單書目收藏:0
本篇論文是利用二進位搜尋演算法電路控制器加快鎖定頻率速度,並利用數位類比轉換器以及整流器來實現寬頻率調變範圍之全數位式鎖頻迴路。其控制電壓範圍由0.7伏至1.6伏,使得頻率調變範圍由30MHz至480NMHz。其中本篇論文使用之電壓控制震盪器在操作頻率480MHz下時其RMS jitter小於0.21%,並使用台積電0.18微米製程其總晶片面積為0.31平方毫米。
This paper proposes a wide frequency tune range all-digital frequency locked loop (ADFLL) with a successive approximation register-controlled (SAR) architecture. It uses a digital to voltage converter (DAC) and regulator to provide a wide supply voltage range from 0.8v to 1.6v for a wide operational tune frequency range of 30MHz
to 480MHz. The proposed voltage controlled oscillator (VCO) performance has a less than 0.21% RMS jitter at 480 MHz output frequency. The core area of ADFLL is 0.31mm2 in a 0.18μm CMOS process.
第一章 緒論 1
1.1. 研究動機與目的 1
1.2. 論文章節架構 1
第二章 先前技術探討 3
2.1. 基本鎖相迴路簡介 3
2.1.1. 線性式鎖相迴路 3
2.1.2. 數位式鎖相迴路 4
2.1.3. 全數位式鎖相迴路 5
2.2. DVD燒錄器寫入時脈訊號產生器 6
2.3. 電流式數位振盪器之全數位鎖相迴路架構介紹 9
2.3.1. 基本系統架構 9
2.3.2. 系統操作模式 10
2.3.3. 數位控制振盪器單元 11
2.4. 新型增益產生器之全數位式鎖相迴路 13
2.5. 相位平均迴路之全數位式鎖相迴路 15
2.6. 寬範圍電壓操作之全數位式鎖相迴路 15
2.7. 基本數位控制延遲元件簡介 17
2.7.1. 分流電容式延遲元件簡介 17
2.7.2. 可變阻抗式延遲元件簡介 18
2.7.3. 電流需求一式延遲元件簡介 19
2.7.4. 電流需求二式延遲元件簡介 20
2.8. 環型震盪器簡介 20
2.8.1. 單端式環型振盪器 21
2.8.2. 負延遲元件振盪器 22
2.8.3. 改良式耦合振盪器 23
2.8.4. 具有次回授迴路之環型振盪器 24
2.8.5. 5級相位環型振盪器 25
2.8.6. 偶數級環形震盪器 26
第三章 全數位偶數級相位鎖頻迴路 28
3.1. 電路架構 28
3.2. 連續近似暫存器控制搜尋法 29
3.2.1. 11位元連續近似暫存器控制電路 30
3.2.2. 11位元環型計數器 31
3.2.3. 12位元2補數加減法器 32
3.2.4. 11位元暫存器 33
3.3. 8位元頻率比數器 34
3.4. 11位元數位類比轉換器 35
3.5. 全擺幅轉換器 38
3.6. 電壓控制振盪器 38
3.7. 時脈訊號結合邏輯電路 43
第四章 電路佈局與模擬 44
4.1. 電路佈局 44
4.1.1. 電壓控制震盪器佈局 44
4.1.2. 11位元電流電壓轉換器 46
4.1.3. 整流器電路佈局 47
4.1.4. 電流源參考電路 47
4.1.5. 其它數位電路 48
4.1.6. 全電路佈局 49
4.1.7. 晶片打線圖 50
4.2. 模擬結果 52
4.2.1. Pre-sim.模擬結果 52
4.2.2. Post-sim.模擬結果 54
第五章 結論與未來研究方向 58
5.1. 結論 58
5.2. 未來研究方向 58
參考文獻 60

[1]J. Dunning, G. Garcia, J. Lundberg, and E. Nuckolls, ‘‘An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors,’’ IEEE J. Solid-State Circuits, vol. 30, no. 4, pp. 412-422, Apr., 1995.
[2]T.-C. Chao and W. Hwang, ‘‘A 1.7mW all digital phase-locked loop with new gain generator and low power DCO,” in Proc. IEEE Int. Symp. Circuit and Systems, 2006, pp. 4867-4870.
[3]P.-L. Chen, C.-C. Chung, J.-N. Yang, and C.-Y. Lee, ‘‘A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications,’’ IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1275-285, Jun., 2006.
[4]J. A. Tierno, A. V. Rylyakov, and D. J. Friedman, ‘‘A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI,’’ IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 42-51, Jan., 2008.
[5]M. G. Johnson and E. L Hudson, “A variable delay line PLL for CPU coprocessor synchronization,” IEEE J. Solid-State Circuits, vol. 23, no. 5, pp. 1218-1223, Oct., 1988.
[6]M. Saint-Laurent and M. Swaminathan, “A digitally adjustable resistor for path delay characterization in high frequency microprocessors,” in Southwest Symp. Mixed-Signal Design, 2001, pp. 61-64.
[7]M. Maymandi-Nejad and M. Sachdev, “A digitally programmable delay element: Design and analysis,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 5, pp. 871-878, Oct. 2003.
[8]M. Maymandi-Nejad and M. Sachdev, “A monotonic digitally controlled delay element,” IEEE J. Solid-State Circuits, vol. 40, no. 11, pp. 2212-2219, Nov., 2005.
[9]U. Karthaus and S. Schabel, “Write pulse generator for 16X DVD recording with symmetric CMOS inverter ring oscillator,” IEEE J. Solid-State Circuits, vol. 40, no. 11, pp. 2286-2295, Nov., 2005.
[10]S.-J. Lee, B. Kim, and K. Lee, “A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme,” IEEE J. Solid-State Circuits, vol. 32, no. 2, pp. 289-291, .Feb., 1997.
[11]Matsumoto, A.; Sakiyama, S.; Tokunaga, Y.; Morie, T.; Dosho, S., “A design method and developments of a low-power and high-resolution multiphase generation system,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 831-843, Apr., 2008.
[12]L. Sun, T. Kwasniewski, and K. Iniewski, “A quadrature output voltage controlled ring oscillator based on three-stage sub-feedback loops,” in Proc. IEEE Int. Symp. Circuits and Systems, 1999, vol. 2, pp. 176-179.
[13]K.-H. Kim, H.-J. Chung, W.-S. Kim, M. Park, Y.-C. Jang, J.-Y. Kim, H.-W. Park, U. Kang, P. W. Coteus, J.-S. Choi, and C. Kim, “An 8 Gb/s/pin 9.6ns row-cycle 288Mb deca-data rate SDRAM with an I/O error detection scheme,” IEEE J. Solid-State Circuits, vol. 42, no. 1, pp. 193-200, Jan., 2007.
[14]H.-H. Chang and J.-C. Wu, "A 723-MHz 17.2-mW CMOS programmable counter", IEEE J. Solid-State Circuits, vol. 33, no. 10, pp. 1572-1575, Oct., 1998.
[15]S.-H. Lee and H.-J. Park, “A COMS high-speed wide-range programmable counter,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 49, vol. 9, pp. 638-642, Sep., 2002.
[16]Y. Konno, K. Tomioka, Y. Aiba, K. Yamazoe, and B.-S. Song, “A CMOS 1x-16x speed DVD write channel IC,” IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 642-650, Mar., 2006.
[17]S. Dosho , S. Sakiyama , N. Takeda , Y. Tokunaga, and T. Morie, “A PLL for a DVD-16 Write System with 63 Output Phases and 32ps Resolution,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., 2006, pp. 2422-2431.
[18]B. Razavi, Design of analog CMOS integrated circuits, 1st ed. Boston, MA, McGraw-Hill, 2003.
[19]B. Razavi, RF microelectronics, 1st ed. Upper Saddle River, NJ, Prentice Hall, 1998.
[20]B. Razavi, Design of integrated circuits for optical communications, 1st ed. Boston, MA, McGraw-Hill, 2002.
[21]S.-I. Liu and C.-Y. Yang, Phase lock loop, 1st ed. Taichung City, Taiwan, Taiwan, Tsang-Hai book publishing Co., 2006.

QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top