|
[1]J. Dunning, G. Garcia, J. Lundberg, and E. Nuckolls, ‘‘An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors,’’ IEEE J. Solid-State Circuits, vol. 30, no. 4, pp. 412-422, Apr., 1995. [2]T.-C. Chao and W. Hwang, ‘‘A 1.7mW all digital phase-locked loop with new gain generator and low power DCO,” in Proc. IEEE Int. Symp. Circuit and Systems, 2006, pp. 4867-4870. [3]P.-L. Chen, C.-C. Chung, J.-N. Yang, and C.-Y. Lee, ‘‘A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications,’’ IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1275-285, Jun., 2006. [4]J. A. Tierno, A. V. Rylyakov, and D. J. Friedman, ‘‘A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI,’’ IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 42-51, Jan., 2008. [5]M. G. Johnson and E. L Hudson, “A variable delay line PLL for CPU coprocessor synchronization,” IEEE J. Solid-State Circuits, vol. 23, no. 5, pp. 1218-1223, Oct., 1988. [6]M. Saint-Laurent and M. Swaminathan, “A digitally adjustable resistor for path delay characterization in high frequency microprocessors,” in Southwest Symp. Mixed-Signal Design, 2001, pp. 61-64. [7]M. Maymandi-Nejad and M. Sachdev, “A digitally programmable delay element: Design and analysis,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 5, pp. 871-878, Oct. 2003. [8]M. Maymandi-Nejad and M. Sachdev, “A monotonic digitally controlled delay element,” IEEE J. Solid-State Circuits, vol. 40, no. 11, pp. 2212-2219, Nov., 2005. [9]U. Karthaus and S. Schabel, “Write pulse generator for 16X DVD recording with symmetric CMOS inverter ring oscillator,” IEEE J. Solid-State Circuits, vol. 40, no. 11, pp. 2286-2295, Nov., 2005. [10]S.-J. Lee, B. Kim, and K. Lee, “A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme,” IEEE J. Solid-State Circuits, vol. 32, no. 2, pp. 289-291, .Feb., 1997. [11]Matsumoto, A.; Sakiyama, S.; Tokunaga, Y.; Morie, T.; Dosho, S., “A design method and developments of a low-power and high-resolution multiphase generation system,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 831-843, Apr., 2008. [12]L. Sun, T. Kwasniewski, and K. Iniewski, “A quadrature output voltage controlled ring oscillator based on three-stage sub-feedback loops,” in Proc. IEEE Int. Symp. Circuits and Systems, 1999, vol. 2, pp. 176-179. [13]K.-H. Kim, H.-J. Chung, W.-S. Kim, M. Park, Y.-C. Jang, J.-Y. Kim, H.-W. Park, U. Kang, P. W. Coteus, J.-S. Choi, and C. Kim, “An 8 Gb/s/pin 9.6ns row-cycle 288Mb deca-data rate SDRAM with an I/O error detection scheme,” IEEE J. Solid-State Circuits, vol. 42, no. 1, pp. 193-200, Jan., 2007. [14]H.-H. Chang and J.-C. Wu, "A 723-MHz 17.2-mW CMOS programmable counter", IEEE J. Solid-State Circuits, vol. 33, no. 10, pp. 1572-1575, Oct., 1998. [15]S.-H. Lee and H.-J. Park, “A COMS high-speed wide-range programmable counter,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 49, vol. 9, pp. 638-642, Sep., 2002. [16]Y. Konno, K. Tomioka, Y. Aiba, K. Yamazoe, and B.-S. Song, “A CMOS 1x-16x speed DVD write channel IC,” IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 642-650, Mar., 2006. [17]S. Dosho , S. Sakiyama , N. Takeda , Y. Tokunaga, and T. Morie, “A PLL for a DVD-16 Write System with 63 Output Phases and 32ps Resolution,” in IEEE Int. Solid-State Circuits Conf. Tech. Dig., 2006, pp. 2422-2431. [18]B. Razavi, Design of analog CMOS integrated circuits, 1st ed. Boston, MA, McGraw-Hill, 2003. [19]B. Razavi, RF microelectronics, 1st ed. Upper Saddle River, NJ, Prentice Hall, 1998. [20]B. Razavi, Design of integrated circuits for optical communications, 1st ed. Boston, MA, McGraw-Hill, 2002. [21]S.-I. Liu and C.-Y. Yang, Phase lock loop, 1st ed. Taichung City, Taiwan, Taiwan, Tsang-Hai book publishing Co., 2006.
|