臺灣博碩士論文加值系統

近年來醫學科學與超大型積體電路的快速發展，應用在人體內的植入式的電子設備也不斷演進，本篇論文使用MATLAB/SIMLINK來做為此次研究植入式電子設備解調電路在加性白色高斯雜訊(AWGN)通道下的位元錯誤率分析的模擬工具，日後在設計上提供一模擬平台，以提高研發的速度，並提昇整體系統的效率。
目前植入式電子設備發展趨向於微小化並搭配無線方式傳輸訊號，因其為植入式的電路，所以其內部的電源供給，得由外部傳輸電路來提供，因此，本篇論文便利用具有低功率且易晶片化的數位PSK解調器來做為分析的對象。其在外部傳送端只有資料訊號是被傳送的，而時脈週期訊號並沒有被傳送，故本論文在內部接收端所採用的數位PSK解調器，使用由接收的資料訊號來產生內部所需要的時脈週期訊號，做為時脈週期訊號的重建；由於其為植入式電路，必須在所接收的資料訊號中，產生其植入電路所須的所有電源，故在傳送端設計一與Q(品質因數)無關的CALSS E功率放大器PSK調變電路，可使其網路有效儲存的能量高或是網路消耗的功率小，達到低功率的消耗，但也因此增加了對解調的困難性，所以對整體的解調設計須再做更複雜的設計，因此建立一個模擬測試平台，將可大大的幫助整個系統的研發速度及效率。

In recent years the science of biomedicine and the VLSI technology have fast development. Biomedical electronic devices which are used to be implanted in the human body have been developed. This paper uses MATLAB/SIMLINK for researching the demodulation circuits in Additive white Gaussian noise (AWGN) channel and the bit error rate (BER) of it. This thesis provides an analysis platform for further optimization and future design of the PSK demodulator for wirelessly implantable electronics.

At present, the types of the implantable electronic devices tend to small and match the wireless way transmission techniques. Because the circuit is implanted, its internal power supply may be provided externally. Therefore, this paper takes focuses on the digital PSK demodulator with low power and small chip area.

External transmitter transmits data only, while the clock is not transmitted. The PSK demodulator regains clock signal at the receiver by the incoming data envelope. Because the system with the PSK demodulator is implanted, a Q (quality factor)-independent CALSS-E power amplifier is designed PSK modulator in the transmitter. It can be effective to the high energy stored in the network, meaning the power consumption is small, and therefore increasing the demodulation difficulty. So the demodulator must be designed to be more complex. Therefore establishing a simulation test platform can greatly help the overall system’s research and facilitate development speed and efficiency.

摘要 ii
Abstract iii
致謝 iv
目錄 v
圖目錄 vii
表目錄 ix
第一章 緒論 1
1.1 研究背景 1
1.2 研究動機 2
1.3 論文架構 3
第二章 解變技術介紹與PSK解調器 4
2.1 調變技術及種類 4
2.1.1 類比調變 4
2.1.2 數位調變 7
2.2 PSK解調器電路架構及工作原理 11
2.2.1 PSK解調器工作原理 12
2.2.2 PSK解調器電路之SIMULINK模擬說明 16
第三章 與Q無關的CLASS E功率放大器PSK調變器設計與原理 19
3.1 功率放大器的種類 19
3.2 CLASS E功率放大器PSK調變器的設計 25
3.3 與Q無關CLASS E功率放大器PSK調變器設計與原理 32
3.3.1 與Q無關CLASS E功率放大器PSK調變器原理 32
3.3.2 與Q無關CALSS E功率放大器PSK調變器設計與模擬 37
第四章 與Q無關之PSK解調設計與位元錯誤率分析 41
4.1 與Q無關之PSK解調設計 41
4.2 BPSK調變之位元錯誤率 49
4.3 與Q無關BPSK調變之位元錯誤率分析 53
4.3.1 與Q無關BPSK調變/解調SIMULINK模擬說明 53
4.3.2 Eb/No與SNR之間的關系 56
4.3.3 位元錯誤率(BER)分析 58
第五章 結論與未來展望 64
5.1 結論 64
5.2 未來展望 65
參考文獻 66

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