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研究生:黃雲
研究生(外文):Yun Huang
論文名稱:4ACE:雙層雙通道之陣列電容平衡繞線器
論文名稱(外文):4ACE:A Double-layer Double-channel Array Capacitance Equilibrium Router
指導教授:陳竹一
指導教授(外文):Jwu-E Chen
學位類別:碩士
校院名稱:國立中央大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:101
語文別:中文
論文頁數:42
中文關鍵詞:電容繞線
外文關鍵詞:routerroutingcapacitorcapacitance
相關次數:
  • 被引用被引用:1
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隨著半導體的製程日漸縮小,製程上的變異在電路效能上的影響也越來越顯著,這也導致了設計上的高複雜度及高時間成本,因此,佈局自動化也就成為類比電路設計的一個重要角色。

在許多類比積體電路,如數位類比轉換器,它的效能往往取決於電容比的精確度;一般來說,電容不匹配的來源可分成兩種:隨機的不匹配及系統的不匹配,隨機的不匹配來自於製程上的變異,相較之下,系統的不匹配則是由佈局的不對稱和製程梯度所影響,這些都會造成整個電路的準確度下降以及良率的降低;為了降低這些負面影響,設計上大都會以並聯多顆較小的單位電容來取代一顆大電容,並同時考慮單位電容間的繞線所帶來的寄生效應。

本論文提出一種同時使用水平及垂直通道的繞線方法來應用於電容陣列的佈局上。依序透過四個步驟: 初始設定、電容擺放、導線建立及寄生電容與補償,便可建立整個電容陣列的佈局繞線,對於包含多個特定電容的陣列以此方法也能完成自動化繞線。在後面的章節會舉出各種不同的特定電容比值之電容陣列的例子,第一組數據是兩個特定電容比值為1:1之電容分壓器,第二組數據是連續電容比值且較懸殊的SARADC電容陣列,最後一組則提出非整數單位電容來驗證可提供精確至小數點後兩位的精確電容比。在整個佈局完成後,最後會透過Calibre來萃取繞線產生的寄生電容,並計算其電容比值,以及測量繞線加上單位電容的面積,來與只使用單一通道的繞線方法來比較。

As the shrink of semiconductor process, the process variation effects performance of circuit much more seriously. It also causes high complexity and time-consuming on designing circuits. Therefore, layout automation is likely to play a key role in analog circuit design.
The performance of many types of analog circuits, like ADC, DAC, etc., relies on the implementation of accurate capacitor ratio. Generally, capacitor mismatch can result from two sources of error: random mismatch and system mismatch. Random mismatch is due to process variation, while system mismatch is mainly caused by asymmetrical layout and processing gradient. These will decrease the accuracy and yield of circuits. To reduce these negative effects, several smaller unit capacitors will be parallel connected to replace the whole bigger capacitor. The parasitic effect between each unit capacitor will also be considered.
In this thesis, a double-layer double-channel array capacitance equilibrium router is proposed for capacitor array block creation. By four steps: initial setting, capacitor placement, generation of interconnects, parasitic capacitor and compensation, the whole routing of circuit will be established. The router can be not only applied to the case of a pair of two target but also to the multiple target capacitors. By the conjunction of an array assignment using of spatial correlation feature, three cases are used as examples to demonstrate the assignment-routing flow. The first one is a case of two targets with a ratio of 1:1. The second one is a case of multiple targets with continuous ratio of 8:4:2:1:1. The last one is a case with non-integer ratio and compensation from parasitic effect, it also can provide an accurate ratio up to second digit after decimal point. After finishing layout creation, the wire parasitic capacitor will be extracted from Calibre. Finally, the accuracy of capacitor ratio and layout area will contrasted with a yield-aware ratio-keeping channel router which uses only vertical channel.

中文摘要………………………………………………………………………………i
Abstract.……………………………………………………………………………....ii
誌 謝………………………………………………………………………………...iii
目 錄………………………………………………………………………………...iv
圖目錄………………………………………………………………………………...vi
表目錄………………………………………………………………………………..vii
第一章 緒論.………………………………………………………………………….1
1.1 動機與背景………………………………………………………………….1
1.2 論文組織…………………………………………………………………….3
第二章 電容佈局設計的概念………………………………………………………..4
2.1 電容簡介…………………………………………………………………….4
2.2 電容不匹配的原因………………………………………………………….7
2.3 電容匹配的提升…………………………………………………………….9
第三章 電容陣列的繞線……………………………………………………………12
3.1 繞線 (Routing) …………………………………………………………....12
3.2 4ACE……………………………………………………………………....13
3.2.1 初始設定…………………………………………………………....14
3.2.2 電容擺放…………………………………………………………....15
3.2.3 4ACE 導線建立流程……………………….……………………...16
3.3 繞線帶來的影響…………………………………………………………...20
3.3.1 導線寄生電容值的評估………………………………….………...20
3.3.2 降低導線寄生電容影響………………………………….………...22
3.4 非整數單位電容…………………………………………………………...23
第四章 實驗及分析………………………………………………………………....26
4.1 自動化佈局繞線…………………………………………………………...26
4.2 電容比值與寄生電容……………………………………………………...29
4.2.1 電容分壓器……………………………………………………….....29
4.2.2 SARADC………….…………………………………………….........32
4.2.3 非整數電容比……….……..…………………………………..........37
第五章 結論…………………………………………………....................................40
參考文獻…………………………………………………..........................................41

[1] X. Jinjun, V. Zolotov, and H. Lei, “Robust Extraction of Spatial Correlation,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 193-202, Apr. 2007.
[2] A. Hastings and R. A. Hastings, The Art of Analog Layout, Prentice Hall, 2000.
[3] M. J. McNutt, S. LeMarquis, and J. L. Dunkley, “Systematic Capacitance Matching Errors and Corrective Layout Procedures,” IEEE Journal Solid-State Circuits, pp. 611-616, May 1994.
[4] P. W. Luo, J. E Chen, C. L. Wey, L. C. Cheng, J. J. Chen and W. C. Wu, “Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 2097-2101, Nov. 2008.
[5] J. E Chen, P. W. Luo and C. L. Wey, “Yield evaluation of analog placement with arbitrary capacitor ratio,” IEEE International Symposium on Quality of Electronic Design, pp. 179-184, Mar. 2009.
[6] J. E Chen, H. C Tseng, C. Long Wey and C. C Huang, “A Yield-aware Ratio-keeping Channel Router for Capacitor Array Block Creation,”
[7] D. Khalil and M. Dessouky. “Automatic Generation of Common-Centroid Capacitor Arrays with Arbitrary Capacitor Ratio,” Proceedings of Design, Automation and Test in Europe Conference and Exhibition, pp. 576-580, Mar. 2002.
[8] M. F Lan, A. Tammineedi and R. Geiger. “Current Mirror Layout Strategies for Enhancing Matching Performance,” Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers, pp. 9-26, Jul. 2001.
[9] C. S. G. Conroy, W. A. Lane, and M. A. Moran, “Statistical Design Techniques for D/A Converters,” IEEE Journal of Solid-State Circuits, pp. 1118-1128, Aug 1989.
[10] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching properties of MOS transistors,” IEEE Journal of Solid-State Circuits, pp. 1433-1439, Oct 1989
[11] W. H Hsiao, Y. T He, Mark P. H Lin, R. G Chang, S. Y Lee , "Automatic common-centroid layout generation for binary-weighted capacitors in charge-scaling DAC," Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2012 International Conference on , vol., no., pp.173-176, 19-21 Sept. 2012
[12] K. H Ho, H. C Ou, Y. W Chang, and H. F Tsao, “Capacitor-Array Routing for Analog Circuit Designs,” 2012
[13] M. M Ozdal, R. F Hentschke, "Exact route matching algorithms for analog and mixed signal integrated circuits," Computer-Aided Design - Digest of Technical Papers, 2009. ICCAD 2009. IEEE/ACM International Conference on , vol., no., pp.231-238, 2-5 Nov. 2009
[14] Laker User Guide and Tutorial, Nov. 2003.
[15] Laker TCL Reference, Nov. 2003.
[16] B. Razavi, Design of Analog CMOS Integrated Circuits, Mcgraw-Hill, 2001.
[17] Clif Flynt, Tcl/Tk: A Developer's Guide, Morgan Kaufmann, 2003.

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