跳到主要內容

臺灣博碩士論文加值系統

(18.97.9.172) 您好!臺灣時間:2025/01/16 05:54
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:何凱倫
研究生(外文):Kai-Lun He
論文名稱:使用FinFET元件並結合電源閘控及匹配線分段技術的內容可定址記憶體之設計
論文名稱(外文):Design of Content-Addressable Memories Using FinFET Devices and Combining Power-Gating with Segmented Match-Line Techniques
指導教授:張孟洲
指導教授(外文):Meng-Chou Chang
學位類別:碩士
校院名稱:國立彰化師範大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2014
畢業學年度:102
語文別:中文
論文頁數:76
中文關鍵詞:內容可定址記憶體FinFET元件電源閘控匹配線分段
外文關鍵詞:Content-addressable memoryFinFET devicesPower-gatingSegmented match-line
相關次數:
  • 被引用被引用:0
  • 點閱點閱:336
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
內容可定址記憶體(Content-Addressable Memory;CAM)是一種允許平行搜尋資料的記憶體結構,可應用於網路路由器的位址搜尋、快取記憶體、資料壓縮、影像處理等等。由於傳統planar MOSFET有嚴重的漏電流功率消耗問題,因此在32nm以下的先進半導體製程,FinFET元件被認為是用來實現VLSI電路設計的更好選擇。本論文共分為三個部份,在第一部份我們提出了六種使用FinFET元件設計的TCAM cells,我們發現其中的Config-LPSG1 FinFET TCAM cell,所消耗的能量在六種架構中最低,比起Config-SG架構,可以節省35%的功率消耗,以及改善30%的能量延遲積。
在論文的第二部分,我們以Config-LPSG1架構為基礎,設計出兩種新型式結合Power-gating技術的FinFET TCAM cells,分別取名為DPG-17T和DPG-16T。其優點是當TCAM cell為“don’t care”狀態時,可以有效的減少漏電流與漏電功耗,並且在匹配線(ML)的放電路徑上,從原本的兩顆電晶體改為一顆電晶體取代,而大幅的提升TCAM搜尋速度。由模擬結果顯示,DPG-17T和DPG-16T架構分別可以減少29.8%和31.7%的功率消耗,並且能改善66.6%和67.4%的能量延遲積。
CAM在搜尋比對的過程中,ML會頻繁的被充放電,而造成大量的動態功率消耗,為了改善這個問題,在論文第三部分我們提出匹配線分段技術,利用傳輸閘當作開關將ML分段,根據不同長度的遮罩位元資料(Mask bits),動態調整ML充電的長度。我們將前兩部分所提出的架構,結合匹配線分段的技術,發現在ML均勻分八段時,Config-LPSG1、DPG-17T和DPG-16T比起原來不分段的架構,分別可以省下45.9%、31.9%和30.7%的功率消耗;在ML變動分三段時,則分別可以省下46.8%、35.4%和34.3%的功率消耗。在ML變動分兩段時,擁有最小的能量延遲積(性能最佳),這三種架構分別可以改善約39.9%、24.4%和23.1%的能量延遲積,為匹配線最佳的分段方式。

Content-addressable memory (CAM) compares input search data in parallel against a table of stored data, and returns the address of the matching data. CAMs can be used in a wide variety of applications requiring high-speed parallel search. These applications include pattern recognition, data compression, and network address translation. As the feature size continues to shrink and the corresponding transistor density increases, the planar MOSFET suffer from the increased subthershold and gate leakage currents. FinFET is considered as one of the best substitutes for planar MOSFET technology in the sub-32 nm regime. This thesis is organized as three parts. In the first part of this thesis, we employed FinFET to design six FinFET TCAM cells, and we found that Config-LPSG1 TCAM cell is the best configuration. Compared with the base TCAM cell, Config-LPSG1 can reduce the power dissipation of the TCAM by 35%, and improve the energy-delay product by 30%.
In the second part of this thesis, we present two novel dynamically power-gated FinFET TCAM cells, called DPG-17T and DPG-16T, which can reduce the static power dissipation of the TCAM cells storing a“don’t care”bit. Moreover, the discharge path of the match-line in DPG-17T/ DPG-16T can be constructed with only one FinFET instead of two FinFETs, greatly boosting the search speed. Simulation results have shown that using DPG-17T/DPG-16T can reduce the average power by 29.8%/31.7% and improve the energy-delay product by 66.6%/67.4%.
In the third part of this thesis, we combined power-gating with segmented match-line techniques to design the FinFET TCAM cells. In this scheme, a match-line is divided into many segments, and a transmission gate is placed between two adjacent segments to control whether the two adjacent segments are connected or disconnected. The mask bits of a stored CAM word dynamically control the operation of transmission gates on the associated match-line, and thus the number of match-line segments involved in precharge/discharge is dynamically determined by the prefix length of the stored CAM word. The shorter the prefix length is, the smaller number of segments involves in precharge/discharge, and the less power dissipates. Simulation results have shown that Config-LPSG1/DPG-17T/DPG-16T combining segmented match-line techniques can effectively reduce the average power and improve the energy-delay product.

中文摘要 i
Abstract ii
目錄 v
圖目錄 vii
表目錄 ix
第一章 緒論 1
1-1 研究背景 1
1-1-1 內容可定址記憶體 1
1-1-2 漏電流與電源閘控技術 3
1-2 研究動機 6
1-3 論文結構 7
第二章 內容可定址記憶體簡介 8
2-1 CAM架構介紹 8
2-2 內容可定址記憶體單元 10
2-2-1 Binary CAM cell 10
2-2-2 Ternary CAM cell 13
2-2-3 NAND-type CAM versus NOR-type CAM 18
第三章 FinFET電晶體元件模型 19
3-1 FinFET電晶體元件模式 19
3-2 使用FinFET電晶體元件設計SRAM的例子 22
第四章 使用FinFET電晶體元件設計的TCAM cells 25
4-1 三種單一組態的FinFET TCAM cells 25
4-1-1 Config-SG FinFET TCAM cell 26
4-1-2 Config-IG FinFET TCAM cell 27
4-1-3 Config-LP FinFET TCAM cell 28
4-2 三種結合多組態的FinFET TCAM cells 29
4-2-1 Config-LPSG1 FinFET TCAM cell 29
4-2-2 Config-LPSG2 FinFET TCAM cell 30
4-2-3 Config-LPSG3 FinFET TCAM cell 31
4-3 實驗模擬結果分析 32
4-3-1 平均功耗、搜尋延遲時間、能量模擬分析 33
4-3-2 不同的搜尋頻率模擬分析 34
第五章 結合Power-gating技術的FinFET TCAM cells 37
5-1 第一種結合Power-gating的FinFET TCAM cell(DPG-17T) 38
5-2 第二種結合Power-gating的FinFET TCAM cell(DPG-16T) 40
5-3 實驗模擬結果分析 41
5-3-1 平均功耗、搜尋延遲時間、能量模擬分析 42
5-3-2 漏電流與漏電功耗模擬分析 44
5-3-3 不同的搜尋頻率模擬分析 46
第六章 結合Power-gating與匹配線分段技術的FinFET TCAM cells 49
6-1 匹配線的分段方式與原理 50
6-1-1 匹配線分段的原理 50
6-1-2 均勻長度分段與變動長度分段 51
6-2 結合匹配線分段技術的FinFET TCAM cells 54
6-2-1 六種結合匹配線分段技術的FinFET TCAM cells 55
6-2-2 兩種結合Power-gating與匹配線分段技術的FinFET TCAM cells59
6-3 實驗模擬結果分析 63
第七章 結論 69
參考文獻 71


圖目錄
圖1:Power-gating三種擺置sleep transistor的方法 (a)PMOS Gating(b)NMOS Gating(c)Dual Gating(圖片摘自[48]) 5
圖2.1.1:具有(a)整體遮罩(Global masking)(b)局部遮罩(Local masking)的TCAM搜尋運作示意圖 9
圖2.1.2:傳統CAM架構方塊圖 10
圖2.2.1:BCAM cell基本結構示意圖 11
圖2.2.2:(a)9T NAND-type(b)10T NAND-type BCAM核心單元電路圖 11
圖2.2.3:(a)9T NOR-type(b)10T NOR-type BCAM核心單元電路圖 12
圖2.2.4:16T NAND-type TCAM核心單元電路圖 15
圖2.2.5:16T NOR-type的(a)Symmetric對稱式(或稱為horizontal水平式) (b)Asymmetric非對稱式(或稱為vertical垂直式)TCAM核心單元電路圖 16
圖2.2.6:(a)NOR-type CAM(b)NAND-type CAM的Match-Line放電路徑示意圖 18
圖3.1.1:(a)Shorted-gate FinFET元件架構圖(b)Independent-gate FinFET元件架構圖(c)32nm independent-gate FinFET元件截面圖(摘自[41]) 20
圖3.1.2:(a)Shorted-gate FinFET元件(b)Independent-gate FinFET元件 21
圖3.1.3:FinFET元件的三種運作模式:(a)SG模式(b)IG模式(c)LP模式 21
圖3.2.1:第一種6T FinFET SRAM cell [41] 23
圖3.2.2:第二種6T FinFET SRAM cell [41] 24
圖4.1.1:Config-SG FinFET TCAM cell電路圖 26
圖4.1.2:Config-IG FinFET TCAM cell電路圖 27
圖4.1.3:Config-LP FinFET TCAM cell電路圖 28
圖4.2.1:Config-LPSG1 FinFET TCAM cell電路圖 30
圖4.2.2:Config-LPSG2 FinFET TCAM cell電路圖 31
圖4.2.3:Config-LPSG3 FinFET TCAM cell電路圖 32
圖4.3:在不同的搜尋頻率,六種FinFET TCAM陣列的功率消耗比較圖 35
圖5.1:Config-LPSG1 FinFET TCAM cell電路圖 38
圖5.2:DPG-17T FinFET TCAM cell電路圖 39
圖5.3:DPG-16T FinFET TCAM cell電路圖 40
圖5.4:在不同的搜尋頻率,三種FinFET TCAM陣列的功率消耗比較圖 48
圖6.1.1:匹配線(ML)的均勻長度分段方式 52
圖6.1.2:2013/11/14 AS2.0 IPv6 BGP 的字首長度分布比率圖 53
圖6.2.1:TCAM cell結合匹配線分段技術的電路圖 54
圖6.2.2:TCAM cell結合匹配線分段技術的周邊電路圖 55
圖6.3.1:在不同搜尋頻率與分段段數,Config-LPSG1架構的功率消耗比較圖 66
圖6.3.2:在不同搜尋頻率與分段段數,DPG-17T架構的功率消耗比較圖 67
圖6.3.3:在不同搜尋頻率與分段段數,DPG-16T架構的功率消耗比較圖 67


表目錄
表2-1:10T NOR-type BCAM cell比對表 13
表2-2:16T NAND-type TCAM cell比對表 15
表2-3:16T NOR-type Symmetric TCAM cell比對表 17
表4-1:六種FinFET TCAM cells使用PTM的32nm FinFET製程 模擬一個64-word×128-bit TCAM陣列,搜尋頻率為3.0 GHz(註:f=e-15;a=e-18) 33
表4-2:六種FinFET TCAM cells使用PTM的32nm FinFET製程 模擬一個64-word×128-bit TCAM陣列,搜尋頻率為2.5 GHz(T= 0.4ns) 34
表4-3:六種FinFET TCAM cells使用PTM的32nm FinFET製程 模擬一個64-word×128-bit TCAM陣列,搜尋頻率為3.5 GHz(T= 0.29ns) 34
表4-4:六種FinFET TCAM cells使用PTM的32nm FinFET製程 模擬一個64-word×128-bit TCAM陣列,搜尋頻率為4GHz(T= 0.25ns) 35
表5-1:三種FinFET TCAM cells使用PTM的32nm FinFET製程 模擬一個64-word×128-bit TCAM陣列,搜尋頻率為4.0 GHz(註:f=e-15;a=e-18) 42
表5-2:三種FinFET TCAM cells在“X”(don’t care) 內部每一顆電晶體的次臨界漏電流(Isub)與漏電功耗(Pleak) 44
表5-3:三種FinFET TCAM cells的整體靜態功率消耗 使用PTM的32nm FinFET製程,模擬一個64-word×128-bit TCAM陣列 45
表5-4:三種FinFET TCAM cells使用PTM的32nm FinFET製程 模擬一個64-word×128-bit TCAM陣列,搜尋頻率為2.5 GHz(T= 0.4ns) 46
表5-5:三種FinFET TCAM cells使用PTM的32nm FinFET製程 模擬一個64-word×128-bit TCAM陣列,搜尋頻率為3 GHz(T= 0.33ns) 46
表5-6:三種FinFET TCAM cells使用PTM的32nm FinFET製程 模擬一個64-word×128-bit TCAM陣列,搜尋頻率為3.5 GHz(T= 0.29ns) 46
表5-7:三種FinFET TCAM cells使用PTM的32nm FinFET製程 模擬一個64-word×128-bit TCAM陣列,搜尋頻率為4.5 GHz(T= 0.22ns) 47
表5-8:三種FinFET TCAM cells使用PTM的32nm FinFET製程 模擬一個64-word×128-bit TCAM陣列,搜尋頻率為5 GHz(T= 0.2ns) 47
表5-9:三種FinFET TCAM cells使用PTM的32nm FinFET製程 模擬一個64-word×128-bit TCAM陣列,搜尋頻率為5.5 GHz(T= 0.18ns) 47
表6-1:IPv4的子網路遮罩範例 51
表6-2:傳輸閘在不同遮罩資料(M和M¯¯)情況下的狀態 54
表6-3:六種FinFET TCAM cells使用PTM的32nm FinFET製程 模擬一個64-word×128-bit TCAM陣列,搜尋頻率為3 GHz(T= 0.33ns) 57
表6-4:六種FinFET TCAM cells使用PTM的32nm FinFET製程 模擬一個64-word×128-bit TCAM陣列,搜尋頻率為3 GHz(T= 0.33ns) 57
表6-5:六種FinFET TCAM cells使用PTM的32nm FinFET製程 模擬一個64-word×128-bit TCAM陣列,搜尋頻率為3 GHz(T= 0.33ns) 58
表6-6:六種FinFET TCAM cells使用PTM的32nm FinFET製程 模擬一個64-word×128-bit TCAM陣列,搜尋頻率為3 GHz(T= 0.33ns) 59
表6-7:三種FinFET TCAM cells使用PTM的32nm FinFET製程 模擬一個64-word×128-bit TCAM陣列,搜尋頻率為4 GHz(T= 0.25ns) 60
表6-8:三種FinFET TCAM cells使用PTM的32nm FinFET製程 模擬一個64-word×128-bit TCAM陣列,搜尋頻率為4 GHz(T= 0.25ns) 60
表6-9:三種FinFET TCAM cells使用PTM的32nm FinFET製程 模擬一個64-word×128-bit TCAM陣列,搜尋頻率為4 GHz(T= 0.25ns) 61
表6-10:三種FinFET TCAM cells使用PTM的32nm FinFET製程 模擬一個64-word×128-bit TCAM陣列,搜尋頻率為4 GHz(T= 0.25ns) 62
表6-11:三種FinFET TCAM cells使用PTM的32nm FinFET製程 模擬一個64-word×128-bit TCAM陣列,搜尋頻率為4 GHz(T= 0.25ns) 62
表6-12:三種FinFET TCAM cells使用PTM的32nm FinFET製程 模擬一個64-word×128-bit TCAM陣列,搜尋頻率為4 GHz(T= 0.25ns) 62
表6-13:三種FinFET TCAM cells使用PTM的32nm FinFET製程 模擬一個64-word×128-bit TCAM陣列,搜尋頻率為2.5 GHz(T= 0.4ns) 63
表6-14:三種FinFET TCAM cells使用PTM的32nm FinFET製程 模擬一個64-word×128-bit TCAM陣列,搜尋頻率為3 GHz(T= 0.33ns) 64
表6-15:三種FinFET TCAM cells使用PTM的32nm FinFET製程 模擬一個64-word×128-bit TCAM陣列,搜尋頻率為3.5 GHz(T= 0.29ns) 64
表6-16:三種FinFET TCAM cells使用PTM的32nm FinFET製程 模擬一個64-word×128-bit TCAM陣列,搜尋頻率為4.5 GHz(T= 0.22ns) 65
表6-17:三種FinFET TCAM cells使用PTM的32nm FinFET製程 模擬一個64-word×128-bit TCAM陣列,搜尋頻率為5 GHz(T= 0.2ns) 65
表6-18:三種FinFET TCAM cells使用PTM的32nm FinFET製程 模擬一個64-word×128-bit TCAM陣列,搜尋頻率為5.5 GHz(T= 0.18ns) 66


[1] S. Rupak, S. Jason and M. Rabi, “Dynamic aggregation of virtual addresses in TLB using TCAM cells,” in Proc. the 21st International Conference on VLSI Design, 2008, pp. 243-248.
[2] Y. Lee, T. Lee, S. An and Y. Lee, “Indirectly-compared cache tag memory using a shared tag in a TLB,” Electronics Letters, vol. 33, no. 21, pp. 1764-1766, 1997.
[3] J.-H. Choi, J.-H. Lee, S.-W. Jeong, S.-D. Kim and C. Weems, “A low power TLB structure for embedded systems,” the Computer Architecture Letters, vol. 1, no. 1, pp. 3, 2002.
[4] B.-W.-Y. Wei, R. Tamer, J.-S. Kim and K. Ng, “A single chip Lempel-Ziv data compressor,” in Proc. the 1993 IEEE International Symposium on Circuits and Systems(ISCAS), vol. 3, 1993, pp. 1953-1955.
[5] C.-Y. Lee and R.-Y. Yang, “High-throughput data compressor designs using content addressable memory,” in Proc. the IEEE Circuits, Devices and Systems, vol. 142, no. 1, 1995, pp. 69-73.
[6] D. J. Craft, “A fast hardware data compression algorithm and some algorithmic extensions,” IBM Journal of Research and Development, vol. 42, no. 6, pp. 733-746, 1998.
[7] S. Panchanathan and M. Goldberg, “A content-addressable memory architecture for image coding using vector quantization,” IEEE Transactions on Signal Processing, vol. 39, no. 9, pp. 2066-2078, 1991.
[8] A.-J. McAuley and P. Francis, “Fast routing table lookup using CAMs,” in Proc. the IEEE Conference on Computer Communications(INFOCOM '93), vol. 3, 1993, pp. 1382-1391.
[9] N.-F. Huang, W.-E. Chen, J.-Y. Luo and J.-M. Chen, “Design of multi-field IPv6 packet classifiers using ternary CAMs,” in Proc. the IEEE Global Telecommunications Conference(GLOBECOM), vol. 3, 2001, pp. 1877-1881.
[10] G. Qin, S. Ata, I. Oka and C. Fujiwara, “Effective bit selection methods for improving performance of packet classifications on IP routers,” in Proc. the IEEE Global Telecommunications Conference(GLOBECOM), vol. 3, 2002, pp. 2350-2354.
[11] H.-J. Chao, “Next generation routers,” Proc. of the IEEE, vol. 90, no. 9, pp. 1518-1558, 2002.
[12] P. Kostas and S. Ali, “Content-addressable memory (CAM) circuits and architectures: a tutorial and survey,” IEEE Journal of Solid-State Circuits, vol. 41, no. 3, pp. 712-727, Mar. 2006.
[13] I. Arsovski, T. Chandler and S. Ali, “A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme,” IEEE Journal of Solid-State Circuits, vol. 38, no. 1, pp. 155-158, Jan. 2003.
[14] I. Arsovski and S. Ali, “A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories,” IEEE Journal of Solid-State Circuits, vol. 38, no. 11, pp. 1958-1966, Nov. 2003.
[15] N. Mohan, W. Fung, D. Wright and M. Sachdev, “Match Line Sense Amplifiers with Positive Feedback for Low-Power Content Addressable Memories,” in Proc. 2006 IEEE Custom Integrated Circuits Conference, 2006, pp. 297-300.
[16] N. Mohan, W. Fung, D. Wright and M. Sachdev, “A low-power ternary CAM with positive-feedback match-line sense amplifiers,” IEEE Transactions on Circuits and Systems, vol. 56, no. 3, pp. 566-573, 2009.
[17] B.-D. Yang and L.-S. Kim, “A low-power CAM using pulsed NAND-NOR match-line and charge-recycling search-line driver,” IEEE Journal of Solid-State Circuits, vol. 40, no. 8, pp. 1736-1744, Aug. 2005.
[18] K.-H. Cheng, C.-H. Wei and S.-Y. Jiang, “ Static divided word matching line for low-power content addressable memory design,” in Proc. the 2004 International Symposium on Circuits and Systems(ISCAS), vol. 2, May 23-26 2004, pp. 629-32.
[19] P.-T. Huang, W.-K. Chang and W. Hwang, “Low power pre-comparison scheme for NOR-type 10T content addressable memory,” in Proc. IEEE Asia Pacific Conference on Circuits and Systems, Dec. 4-7 2006, pp. 1301-1304.
[20] P. Kostas and S. Ali, “A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme,” IEEE Journal of Solid-State Circuits, vol. 39, no. 9, pp. 1512-1519, Sep. 2004.
[21] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits, ” in Proc. IEEE, vol. 91, no. 2, Feb. 2003, pp.305-327.
[22] N. H. E. Weste and D. M. Harris, Integrated Circuit Design, 4th ed., Pearson Education, 2011, ch.4.
[23] Z. Chen, M. Johnson, L. Wei, and K. Roy, “Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks,” in Proc. Int. Symp. Low Power Electronics and Design, 1998, pp. 239-244.
[24] S. Narendra, S. Borkar, V. De, D. Antoniadis, and A. Chandrakasan, “Scaling of stack effect and its application for leakage reduction,” in Proc. Int. Symp. Low Power Electronics and Design, 2001, pp. 195-200.
[25] Y. Oowaki et al., “A sub-0.1 µm circuit design with substrate-over-biasing,” in Proc. IEEE Int. Solid-State Circuits Conf., 1998, pp. 88-89.
[26] J. Tschanz, J. Kao, S. Narendra, R. Nair, D. Antoniadis, A. Chandrakasan, and V. De, “Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage,” IEEE J. Solid-State Circuits, Vol. 37, No. 11, pp. 1396-1402, Nov. 2002.
[27] C. Neau and K. Roy, “Optimal body bias selection for leakage improvement and process compensation over different technology generations,” in Proc. Int. Symp. Low Power Electronics and Design, Aug. 2003, pp. 116-121.
[28] M. Nomura, Y. Ikenaga, K. Takeda, Y. Nakazawa, Y. Aimoto, and Y. Hagihara, “Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes,” IEEE J. Solid-State Circuits, vol. 41, no. 4, pp.805-814, Apr. 2006.
[29] H. Jeon, Y.-B. Kim, M. Choi, “Standby leakage power reduction technique for nanoscale CMOS VLSI systems,” IEEE Trans. Instrumentation and Measurement, vol. 59, no. 5, pp. 1127-1133, May 2010.
[30] P. Pant, V. K. De, and A. Chatterjee, “Simultaneous power supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits,” IEEE Trans. VLSI Syst., vol. 6, no.4, pp. 538-545, Dec. 1998.
[31] L. Wei, Z. Chen, K. Roy, M. C. Johnson, Y. Ye, and V. K. De, “Design and optimization of dual threshold circuits for low-voltage low-power applications,” IEEE Trans. VLSI Syst., vol. 7, no. 1, pp. 16-24, Mar. 1999.
[32] S. Mutob, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, “1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS,” IEEE J. Solid-State Circuits, vol. 30, no. 8, pp. 847-854, Aug. 1995.
[33] T. Inukai, M. Takamiya, K. Nose, H. Kawaguchi, T. Hiramoto, and T. Sakurai, “Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration,” in Proc. IEEE Custom Integrated Circuits Conf., 2000, pp. 409-412.
[34] H. Kawaguchi, K. Nose, and T. Sakurai, “A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current, ” IEEE J. Solid-State Circuits, vol. 35, no.10, pp. 1498-1501, Oct. 2000.
[35] K. Ishida, K. Kanda, A. Tamtrakarn, H. Kawaguchi, and T. Sakurai, “Managing subthreshold leakage in charge-based analog circuits with low-VTH transistors by analog T- switch (AT-switch) and super cut-off CMOS (SCCMOS),” IEEE J. Solid-State Circuits, vol. 41, no.4, pp. 859-867, Apr. 2006.
[36] T. Kuroda, T. Fujita, T. Nagamatu, S. Yoshioka, T. Sei, K. Matsuo, Y. Hamura, T. Mori, M. Murota, M. Kakumu, and T. Sakurai, “A high-speed low-power 0.3 μm CMOS gate array with variable threshold voltage (VT) scheme,” in Proc. IEEE Custom Integrated Circuits Conf., 1996, pp. 53-56.
[37] K.-S. Min and T. Sakurai, “Zigzag super cut-off CMOS (ZSCCMOS) scheme with self-saturated virtual power lines for subthreshold-leakage-suppressed sub-1-v-vdd LSI’s,” in Proc. European Solid-State Circuits Conf., 2002, pp. 679-682.
[38] M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi, Low Power Methodology Manual: For System-on-Chip Design, Springer Publishing Company, 2007.
[39] E. Nowak et al., “Turning Silicon on Its Edge,” IEEE Circuits &; Device Magazine, pp. 20-31, Jan./Feb. 2004.
[40] M. Agostinelli, M. Alioto, D. Esseni, and L. Selmi, “Leakage-delay tradeoff in FinFET logic circuits: A comparative analysis with bulk technology,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 2, pp. 232–245, Feb. 2010.
[41] S. A. Tawfik, Z. Liu, and V. Kursun, “Independent-gate and tied-gate FinFET SRAM circuits: Design guidelines for reduced area and enhanced stability,” in Proc. ICM, 2007, pp. 171–174.
[42] “Predictive Technology Model (PTM),” http://ptm.asu.edu/
[43] “BGP Routing Table Analysis Reports,” http://bgp.potaroo.net/v6/as2.0/index.html/
[44] P. T. Huang, S. W. Chang, W. Y. Liu, and W. Hwang, “ Green microarchitecture and circuit co-design for ternary content addressable memory,” in Proc. IEEE International Symposium on Circuits and Systems ISCAS, 2008, pp. 3322–3325.
[45] Y.-J. Chang,“Using the Dynamic Power Source Technique to Reduce TCAM Leakage Power,” IEEE Transactions on Circuits and Systems Part II: Express Briefs, Vol.57, pp. 888-892, 2010.
[46] Y.-J. Chang, K.-L. Tsai, H.-J. Tsai,“Low Leakage TCAM for IP Lookup Using Two-Side Self-Gating,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.60, pp. 1478 - 1486, 2013.
[47] S. Baeg,“Low-Power Ternary Content-Addressable Memory Design Using a Segmented Match Line,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.55, pp. 1485 - 1494, 2008.
[48] T. Lin, K. Chong, B. Gwee and J. S. Chang, "Fine-Grained Power Gating for Leakage and Short -Circuit Power Reduction by Using Asynchronous-Logic," IEEE Int. Symp. Circuits and Systems, pp. 3162-3165, May. 2009.
[49] Y.-J. Chang, T.-C. Wu,“A low-power TCAM design using mask-aware match-line (MAML) technique,” in Proc. the 21st Great Lakes Symposium on VLSI, 2011, pp. 109-114.
[50] M.-C. Chang, K.-L. He and Y.-C. Wang, “Design of Asymmetric TCAM (Ternary Content-Addressable Memory) Cells Using FinFET,”accepted, to appear in Proc. 2014 IEEE 3rd Global Conference on Consumer Electronics, 2014.

連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top