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 Probabilistic circuits are very attractive for the next generation ultra-low power designs. It is important to test probabilistic circuits because a defect in probabilistic circuit may increase the erroneous probability. However, there is no suitable fault model and test generation/compression technique for probabilistic circuits yet. In this paper, a probabilistic fault model is proposed for probabilistic circuits. The number of faults is linear to the gate count. A statistical method is proposed to calculate the repetition needed for each test pattern. An integer linear programming (ILP) method is presented to minimize total test length, while keeping the same fault coverage. Experiments on ISCAS’89 benchmark circuits show the total test length of our proposed ILP method is 2.77 times shorter than a greedy method.
 摘要 iAbstract iiTable of Contents iiiList of Figures vList of Tables viChapter 3 Introduction 11.1 Motivation 11.2 Proposed Technique 71.3 Contribution 91.4 Organization 9Chapter 4 Background 102.1 Erroneous Probability Evaluation 102.1.1 Probabilistic Transfer Matrix (PTM) 102.1.2 Probabilistic Gate Model 142.2 Hypothesis Testing 152.2.1 Binomial Distribution 162.2.2 Z-score 172.2.3 Hypothesis Testing 182.3 Previous Work about Probabilistic Circuits 21Chapter 5 Proposed Techniques 253.1 Overall Flow 253.2 Probabilistic Fault Model 263.3 Probabilistic Fault Simulation 283.4 Probabilistic Fault Dictionary 293.4.1 Test Pattern Repetition Translation 303.4.2 Multiple-output Circuits 323.5 Linear Programming Model 343.5.1 Problem Definition 343.5.2 Objective Function and Constraints 353.5.3 Constraints and Terms Analysis 37Chapter 6 Experimental Results 394.1 Experiment Setting and Benchmark Circuits 394.2 Comparison with Greedy Algorithm 414.3 Discussion 42Chapter 7 Conclusion and Future Work 445.1 Conclusion 445.2 Future Work 44References 46
 [Abdollahi 07] Abdollahi, Afshin. "Probabilistic decision diagrams for exact probabilistic analysis." IEEE/ACM international conference on Computer-aided design, 2007.[Cheemalavagu 05] S. Cheemalavagu, P. Korkmaz, K. V. Palem, B. E. S. Akgul, and L. N. Chakrapani, “A probabilistic CMOS switch and its realization by exploiting noise,” In Proc. Int. Conf. Very Large Scale Integr. Syst. Chip (VLSI-SoC), 2005.[CPLEX 14] IBM ILOG CPLEX Optimization Studio Community Edition, https://www-01.ibm.com/software/commerce/optimization/cplex-optimizer/[Du 15] Du, Zidong, et al. "Leveraging the error resilience of neural networks for designing highly energy efficient accelerators." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015.[Hogg 97] Hogg, R.V. and Tanis, E.A. Probability and Statistical Inference, fifth Edition, Prentice-Hall, 1997.[Heydari 00] P. Heydari and M. Pedram. Analysis of jitter due to power-supply noise in phase-locked loops. In Proc. of the IEEE Custom Integrated Circuits Conference, 2000.[Han 05] Han, Jie, et al. "Faults, error bounds and reliability of nanoelectronic circuits." IEEE International Conference on. IEEE, 2005.[Huang 15] Huang, Ching-Yi, et al. "Correctness Analysis and Power Optimization for Probabilistic Boolean Circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015.[ITRS 07] International Technology Roadmap for Semiconductors, “International technology roadmap for semiconductors 2007 edition”.[Kim 03] N. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J. Hu, M. Irwin, M. Kandemir, and V. Narayanan. “Leakage current: Moore’s law meets static power.” IEEE Computer, 2003.[Krishnaswamy 07] Krishnaswamy, Smita, Igor L. Markov, and John P. Hayes. "Tracking uncertainty with probabilistic logic circuit testing." IEEE Design & Test of Computers, 2007.[Kim 14] Kim, Jaeyoon, and Sandip Tiwari. "Inexact computing using probabilistic circuits: Ultra low-power digital processing." ACM Journal on Emerging Technologies in Computing Systems (JETC), 2014.[Kim 16] Kim, Kyounghoon, et al. "Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks." In Proc. of Annual Design Automation Conference, 2016.[McCluskey 00] McCluskey, Edward J., and Chao-Wen Tseng. "Stuck-fault tests vs. actual defects." Test Conference, 2000.[Mendoza 04] F. Mendoza-Hernandez, M. Linares-Aranda, and V. H. Champac-Vilela. “The noise immunity of dynamic digital circuits with technology scaling.” In Proc. of International Symposium on Circuits and Systems (ISCAS), 2004.[NanGate 09] NanGate Open Cell Library. Retrieved from http://www.nangate.com/, 2008.[Patel 03] Patel, Ketan N., Igor L. Markov, and John P. Hayes. "Evaluating circuit reliability under probabilistic gate-level fault models." In Proc. of the International Workshop on Logic and Synthesis, 2003.[Palem 03] K. V. Palem. “Energy aware algorithm design via probabilistic computing: from algorithms and models to Moores law and novel (semiconductor) devices.” In Proc. Intl. Conf. on Compilers, Architecture and Synthesis for Embedded Systems, 2003.[Palem 03] K. V. Palem. “Proof as experiment: Probabilistic algorithms from a thermodynamic perspective.” In Proc. Intl. Symposium on Verification (Theory and Practice), 2003.[Palem 03] K. V. Palem. Proceedings of International Symposium on Verification, 2003.[Palem 12] K. Palem and A. Lingamneni, “What to do about the end of Moore’s law, probably!” In Proc. Annu. Design Autom. Conf., 2012.[RICE 09] http://www3.ntu.edu.sg/home/zhkong/e3%20world%204_26Feb09_final.pdf[Rejimon 09] Rejimon, Thara, Karthikeyan Lingasubramanian, and Sanjukta Bhanja. "Probabilistic error modeling for nano-domain logic circuits." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009.[Sano 00] N. Sano. "Increasing importance of electronic thermal noise in sub-0.1mm Si-MOSFETs." The IEICE Transactions on Electronics, 2000.[Zscore 79] https://en.wikipedia.org/wiki/Standard_score
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