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研究生:唐英軒
研究生(外文):Tang, Ying-Hsuan
論文名稱:以FPGA為基礎之數位相位陣列雷達設計與實現
論文名稱(外文):Design and Implementation of an FPGA Based Digital Phased Array Radar
指導教授:王毓駒陳柏宏陳柏宏引用關係
指導教授(外文):Wang, Yu-JiuChen, Po-Hung
口試委員:朱大舜
口試委員(外文):Chu, Ta Shun
口試日期:2019-05-06
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2019
畢業學年度:107
語文別:英文
論文頁數:37
中文關鍵詞:數位相位陣列雷達
外文關鍵詞:Digital Phased Array Radar
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在雷達的發展中,雷達架構從傳統的機械式雷達向相位陣列雷達演變,相位
陣列雷達有不依賴機械式旋轉來改變掃描方向的優點,因此可以大幅的提高掃描
速度,在相位陣列中分為被動相位陣列、主動相位陣列與數位相位陣列,本論文
選擇數位相位陣列,並以現場可程式化邏輯閘陣列 (FPGA)為基礎來設計與實現,
數位架構的特點在於將前端天線所收到的高頻訊號,在降頻至基頻後交給數位訊
號處理來做訊號相移,以FPGA 來實現數位訊號處理有開發彈性大,並可對任意
天線單元做到精確控制的優勢,本論文將詳述X 頻段256 單元數位相位陣列雷達
的設計與實現。
In the development of radar, the radar architecture evolved from traditional
mechanical radar to phased array radar. The phased array radar has the advantage of
not relying on mechanical rotation to change the scanning direction, so it can greatly
improve the scanning speed in phased array radar. There are three main types of
phased array, passive phased array, active phased array, and digital phased array. This
paper chooses digital phased array, designed and implemented based on field
programmable gate array (FPGA). The digital active phased array is characterized by
using the DSP (digital signal processing) to operate the phase shifting, which the
signal is received and down converted by the transceiver. The advantage of using the
FPGA to implement the DSP is great development flexibility. And the FPGA can
precisely control any antenna element independently. The design and implementation
of X-band 256 elements digital phased array radar will be discussed in detail in this
paper.
1 Introduction 1
2 Phased Array Category 2
2.1 Passive Phased Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2 Active Phased Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.3 Digital Phased Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 X-Band 256 Elements Radar System Architecture 6
3.1 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Tier-1 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2.1 Transceiver Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.2 Transceiver Power Supply Board . . . . . . . . . . . . . . . . . . . . 18
3.2.3 Tier-1 FPGA Board . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.4 Tier-1 FPGA Power Supply Board . . . . . . . . . . . . . . . . . . . 22
3.3 Tier-2 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.1 Tier-1 to Tier-2 Interposer Board . . . . . . . . . . . . . . . . . . . . 24
3.3.2 Tier-2 FPGA Board . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3.3 LO Clock Source Board . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.3.4 AC-DC Power Supply Board . . . . . . . . . . . . . . . . . . . . . . . 30
4 X-Band 256 Elements Radar System Implementation 32
4.1 FPGA Based Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.2 Tier-1 FPGA Digital Signal Processing . . . . . . . . . . . . . . . . . . . . . 33
4.3 Tier-2 FPGA Digital Signal Processing . . . . . . . . . . . . . . . . . . . . . 34
4.4 Transceiver Chip Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5 Conclusion 36
Bibliography 37
Bibliography
[1] A. Hajimiri, A. Komijani, A. Natarajan, R. Chunara, X. Guan and H. Hashemi, "Phased
array systems in silicon," in IEEE Communications Magazine, vol. 42, no. 8, pp. 122-
130, Aug. 2004.
[2] J. S. Herd and M. D. Conway, "The Evolution to Modern Phased Array Architectures,"
in Proceedings of the IEEE, vol. 104, no. 3, pp. 519-529, March 2016.
[3] C. Chu et al., "A fully-integrated Ka-band 4TX/4RX phased-array transceiver IC in
65nm CMOS," 2016 IEEE International Symposium on Radio-Frequency Integration
Technology (RFIT), Taipei, 2016, pp. 1-3.
[4] Y. Kao, H. Chou, C. Peng, Y. Wang, B. Su and T. Chu, "18.3 A single-port duplex
RF front-end for X-band single-antenna FMCW radar in 65nm CMOS," 2017 IEEE
International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2017, pp.
318-319.
[5] K. Hayate, K. Nishimori, T. Hiraguri and H. Makino, "Block diagonalization using FFT
beams at user terminal for implicit beamforming," 2014 IEEE International Workshop
on Electromagnetics (iWEM), Sapporo, 2014, pp. 92-93.
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