臺灣博碩士論文加值系統

本篇論文介紹以TSMC 0.18μm製程所研製而成之射頻前端子電路。其中，下變頻混頻器朝向高轉換增益、良好線性度與低功耗等方向研製；而在上頻混頻器之設計中，主要朝向適當的轉換增益與較高的線性度，最後，結合上變頻(Up-Conversion)、下變頻(Down-Conversion)混頻器與壓控振盪器(VCO)之設計。
在電路設計方面，第一顆晶片為使用負電阻之架構，以不犧牲線性度為前提，來達到較高之轉換增益，主要電路架構基於雙平衡混頻器電路，在轉導級方面引入電流再生(Current-reused)技術及負電阻之架構，來達到高線性度與較高之轉換增益。此電路架構經由實際量測後可獲得10dB之之轉換增益，三階截斷點(IIP3)為-3dBm且在供應電壓為1.3V下時，其DC消耗功率為5.2mW。其整體晶片尺寸大小為0.95mm × 1.02mm。
第二顆晶片為上/下變頻混頻器及結合壓控振盪器之設計，應用於IEEE 802.11a之協定，主要電路架構包含上/下變頻混頻器之主被動負載，有別於傳統將上變頻與下變頻混頻器負載不共用之問題，來達到節省面積與成本之目的；在開關級方面，將LO之Body端接地，以降低開關同時導通時間，來達到較高之轉換增益；在上變頻混頻器之轉導級引入電流再生與Gm-boosted技術，藉以在上變頻混頻器獲得較高之線性度與較高之轉換增益，而在下變頻混頻器之轉導級引入源級退化技術來增加下變頻混頻器之線性度，同時引入傳統型之壓控振盪器，來增加實用性。電路經由實際EM模擬後，壓控振盪器之相位雜訊為-113.6dbc/Hz、輸出功率為-0.9dBm、可調頻率範圍約為19%、功耗為3mW；在上變頻混頻器部分，轉換增益約為7.7dB、 為-7dBm、功耗約為4.37mW、而在下變頻混頻器時，轉換增益為14.5dB、 約為-10.8dBm、消耗功率為2.2mW。其整體晶片尺寸大小為1.394mm × 1.182mm。

Two chip designs of RF down and up conversion mixers are presented in the research paper based on the TSMC 0.18μm CMOS process. There are “A High-Linearity Up-Conversion Mixer Utilizing Negative-Resistance Design” and “A Self-oscillating Down / Up conversion Mixer Design”, respectively. The aims of mixer design tend to high conversion gain and low power consumption while the targets of VCO design are low phase noise and low power consumption.

The proposed circuit of the first chip is a double-balance mixer design with employing current-enhanced and negative-resistance techniques. The current-enhanced technique is applied to the transconductance stage of mixer to improve the conversion gain and linearity. Beside, current-enhanced topology also has the advantage of current bleeding. The designed mixer achieves simulation results that include conversion gain of 10dB and the IIP3 of 3dBm under consuming power of 5.2mW from 1.2 supply voltage. The chip size including pads is 0.95mm × 1.02mm.

The second chip is a design of down/up conversion mixer with build-in VCO for IEEE 802.11a applications. The proposed down/up mixer employs the common load to replace the traditional loads of resistance and inductance, respectively. The conversion gain of mixer is increased by LO body ground technique. Moreover, by using gm-boosting technique, the conversion gain of up conversion mixer is also improved. Simulation results of the proposed mixer exhibit the conversion gain of up/down conversion mixer of 7.7dB and 14.2dB, respectively. The phase noise is -113dBc/Hz and the tuning range of VCO is and 19% while it consumes 3mW from 0.65V supply voltage. The power consumptions of up and down conversion mixers are 4.35mW and 2.53mW from 1.8V supply voltage, respectively. The chip size including pads is 1.394mm × 1.182mm.

摘要 i
ABSTRACT iii
誌謝 v
目錄 vi
表目錄 viii
圖目錄 ix
第一章 序論 1
1.1 研究背景與動機 1
1.2 射頻接收機與發射機架構 2
1.2.1 收發機架構概述 2
1.2.2 外差式接收機架構簡介 4
1.2.3 直接降頻接收機架構簡介 5
1.2.4 直接升頻發射機架構簡介 6
1.2.5 二次升頻發射機架構簡介 7
1.2.6 總結 9
1.3 論文流程與概述 11
第二章 混頻器之原理概述 12
2.1 概述 12
2.2 混頻器之重要性能參數 16
2.2.1 轉換增益 16
2.2.2 線性度 17
2.2.3 雜訊係數 20
2.2.4 隔離度 29
2.3 混頻器之電路架構 30
2.3.1 被動式混頻器與主動式混頻器 30
2.3.2 單端輸出與差動輸出結構 31
2.3.3 單平衡式混頻器 33
2.3.4 雙平衡式混頻器 36
第三章 壓控振盪器之原理概述 39
3.1 振盪原理 39
3.1.1 回授的觀點 39
3.1.2 負電阻的觀點 40
3.2 壓控振盪器之架構 44
3.2.1 環型振盪器 45
3.2.2 LC諧振(LC Tank)振盪器 45
3.3 壓控振盪器性能參數 51
3.3.1 可調頻率範圍(Tuning Range) 51
3.3.2 功率損耗(power consumption) 52
3.3.3 輸出功率(output power) 54
3.3.4 溫度係數 55
3.3.5 諧波失真 55
3.3.6 相位雜訊 56
第四章 上/下變頻混頻器之設計 77
4.1 使用負電阻技術之上變頻混頻器 77
4.1.1 電路架構設計 77
4.1.2 模擬與量測結果 82
4.1.3 實際電路佈局與考量 84
4.1.4 結果與討論 85
4.2 應用於IEEE 802.11a具有內建式振盪器之上/下變頻混頻器 86
4.2.1 電路架構設計 87
4.2.2 模擬結果 96
4.2.3 實際電路佈局與考量 100
4.2.4 結果與討論 101
4.3 設計流程 103
4.4 量測考量 104
第五章 結論與未來展望 105
參考文獻 107
論文著作 110

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