臺灣博碩士論文加值系統

複晶矽薄膜電晶體(poly-Si TFT)因為其優異的元件特性，最近幾年在液晶顯示器(AMLCD)及有機發光二極體(AMOLED)顯示器應用中之所以會是眾所注目的焦點。相較非晶矽薄膜電晶體，複晶矽薄膜電晶體有較高電流趨動能力及較好的可靠度，因此在複晶矽薄膜電晶體顯示器裡，它可以被用來整合畫素電路及周邊驅動電路於同一片玻璃基板上，如此使面板結構簡單化且可以減少週邊半導體零組件的使用數量以及後段模組在組裝時的接點數目，進而提高工程可靠度，除此之外更可降低驅動IC成本，維持低耗電特性，提供高精細的畫質表現。所以，複晶矽薄膜電晶體被視為實現系統化面板(System on Panel)的關鍵技術。
然而不同於畫素的薄膜電晶體，在驅動電路上的薄膜電晶體會受到高頻的閘極脈波電壓所驅動。因此，薄膜晶體在交流訊號操作下的劣化機制必須要仔細的探討。
在這篇論文中，我們研究了低溫複晶矽薄膜電晶體在閘極負偏壓脈波且汲極直流偏壓的劣化，我們觀察到在汲極端會有一個嚴重的劣化，當閘極操作在負偏壓交流訊號且汲極直流偏壓下會量測到一個電流(在此我們稱為pump current)。汲極和源極有不同的電場效應，因此，在此電流經過時，也在這兩端產生不一樣的劣化行為。我們也觀察到元件的劣化和汲極端的電壓、閘極電壓上升時間、閘極電壓下降時間、閘極電壓的範圍很有關係。我們可以用量到的pump current來解釋不同操作情況下對元件的劣化行為。這個發現幫助我們在研究LTPS元件的可靠度上，了解並估計元件的劣化機制並在設計元件上面提供了一個參考。

Polycrystalline silicon (poly-Si) thin film transistors (TFTs) have recently attracted much attention in the application on the integrated peripheral circuits of active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diode (AMOLED) displays. The significant advantages over amorphous silicon (a-Si) TFTs are in the higher current driving capability and the better reliability. In poly-Si TFT-controlled displays, poly-Si TFTs are used to implement pixel circuits and driving circuits on a single glass substrate to reduce system cost and posses compact module. Therefore, the poly-Si TFT is the best candidate to realize system–on–panel (SOP).
However, unlike pixel TFTs, TFTs in driver circuits are subjected to high-frequency voltage pulses. Therefore, the degradation mechanism under dynamic operation should be understood in detail.
In this thesis, the device degradation of low-temperature polycrystalline thin film transistor under gate AC stress in off region with drain bias has been investigated. The effective drain current, pumped by the AC gate voltages in the off region, undergoes different electric field effects near the source and drain junction and therefore results in different degradation behavior near these two regions. It is noticed that the degradation depends profoundly on the DC drain bias. It is also affected by the rising time Tr, falling time Tf, and the Vg range. This finding would be helpful in the understanding and evaluation of the device degradation mechanism and provide a guideline to design for reliability of poly-Si TFT circuit.

Chapter 1 Introduction..................................1
1.1 Overview of Low-Temperature Polycrystalline Silicon
Thin Film Transistors (LTPS TFTs)...................1
1.2 Review of Studies on TFT under DC and AC Stress.....3
1.2.1 DC stress........................................3
1.2.2 AC stress........................................5
1.3 Motivation..........................................12
1.4 Thesis Organization.................................14
Chapter 2 Experiments....................................16
2.1 Procedures of Fabrication of LTPS TFTs..............16
2.2 AC Stress Conditions................................17
2.3 Extraction of Device Electrical Parameters..........21
Chapter 3 AC Stress with Drain Bias Effect...............24
3.1 Degradation of I-V Behavior.........................24
3.1.1 Effect of drain bias.............................24
3.1.2 Damage region....................................26
3.2 Degradation of C-V Behaviors........................29
3.2.1 Slicing circuit model............................29
3.2.2 Gate-source capacitance & gate-drain capacitance.31
3.3 Electric field simulation...........................35
3.4 Off Region AC stress with Drain and Source Bias.....39
3.5 Degradation Model and Pump Current..................43
Chapter 4 Other Effect...................................48
4.1 Duty ratio..........................................48
4.2 Rising time.........................................50
4.3 Falling time........................................55
4.4 Vg range effect.....................................60
Chapter 5 Conclusion.....................................69
References...............................................70
Vita.....................................................73

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