1. M. Annoni, et al, ” Nozzles classification in a high pressure water jet systems,” Proceedings of IEEE Instrumentation and Measurement Technology, pp. 1-6, 2007.
2. M. Annoni, et al, “Measurement and analysis of the signals of a high pressure water jet pump,” Proceedings of IEEE Instrumentation and Measurement Technology, pp. 1311-1316, 2005.
3. P. Yu, et al, “Study of aluminum pad contamination sources during wafer fabrication, shipping, storage and assembly,” High Density packaging and Microsystem Integration, pp. 1-3, 2007.
4. Jianhua Li, et al, “Laser dicing and subsequent die strength enhancement technologies for ultra-thin wafer” Electronic Components and Technology Conference, pp. 761-766, 2007.
5. J. Sillanpaa, “Ultra short pulse laser meeting the requirements for high speed and high quality dicing of low-k wafers,” IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, pp. 194-196, 2005.
6. Z. L. Wang, et al, “300mm low-k wafer dicing saw study,” International Conference on Electronic Packaging Technology, pp. 262-268, 2005.
7. D.Y.R. Chong, et al, “Mechanical characterization in failure strength of silicon dice,” The Ninth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, vol. 2, pp. 203-210, 2004.
8. Betty Yeung, et al, “An overview of experimental methodologies and their applications for die strength measurement,” IEEE Transactions on Components and Packaging Technologies, vol. 26, iss. 2, pp. 423-428, 2003.
9. B.H. Yeung, et al, “Assessment of backside processes through die strength evaluation,” IEEE Transactions on Advanced Packaging, vol. 23, iss. 3, pp. 582-587, 2000
10. M. J. Yim, et al, “Effect of Conductive Particle Properties on the Reliability of Anisotropic Conductive Film for Chip-on-Glass Applications,” IEEE Transactions on Electronics Packaging Manufacturing, vol. 30, iss. 4, pp. 306-312, 2007.
11. M.-D. Ker, “Whole-chip ESD protection design for submicron CMOS VLSI,” IEEE Trans. on Electron Devices, Vol.46.pp.173-183, 1999.
12. S.P. Zhao, et al, “Contamination analyses of Al bond pads using FIB/SEM/EDX,“ 6th International Physical & Failure Analysis of Integrated Circuits, pp. 254 – 259, 1997.
13. 曾建欽,”功率LDMOS ESD破壞故障分析之研究”,大葉大學,電機工程學系碩士班碩士論文,民國91年。14. 施文勝,”運用六標準差手法於液晶顯示器模組COG製程改善之研究”,逢甲大學,工業工程與系統管理研究所碩士論文,民國95年。15. 二澤 正行, “靜電管理入門”, 全華科技圖書股份有限公司, 2005, 初版。
16. 萬其超,電化學之原理與應用,徐氏文教基金會,民國82年,一版。
17. 施敏,半導體元件物理與製作技術,高立圖書有限公司,民國88年,三版。
18. 洪嘉宏、萬遠祖,次世代液晶顯示器製程設備發展趨勢,化合物半導體與光電技術,2005。
19. EIA/JEDEC Standard, Test Method A114-B, Electrostatic Discharge(ESD) Sensitivity Testing Human-Body Model(HBM).
20. EIA/JEDEC Standard, Test Method A115-A, Electrostatic Discharge(ESD) Sensitivity Testing Machine Model(MM).
21. EIA/JEDEC Standard, Test Method C101-C, Electrostatic Discharge(ESD) Sensitivity Testing Charged-Device Model(CDM)