臺灣博碩士論文加值系統

隨著處理圖案影像聲音和資料的科技產品的普遍，一個高效率的電源管理IC越來越顯出其必要性。最普遍的電源管理穩壓器有兩種模式，一個是脈衝寬度調變方式，另一種則是脈衝頻率調變。但是脈衝寬度調變的方式在低負載電流的情況下其的效率是降低的，而脈衝頻率調變則是在高負載電流的情況降低。為了在寬範圍的負載電流下還能維持極高的效率兩種模式的結合是必要的，但是現今所提出的結合多種模式的架構所使用的切換點通常是使用此穩壓器是否進入不連續導通模式與否來做為判定的方法，但是此方法會讓脈衝寬度調變在效率降低一個幅度後才會切換為脈衝頻率調變。所以此方法會降低了效率。此論文提出了一個新的方法來使整個穩壓器在極佳的切換點來做切換，這樣即可在極寬的負載電流下維持很高的效率了。為了降低整個穩壓器所佔的面積，我們還把脈衝寬度調變模式的電路和脈衝頻率調變的電路做了一個結合。為了提高效率，我們還提出了一個動態部份關閉電路的技術，此技術可以動態的關閉不需要電路的偏壓電流。這個穩壓器設計在.35的製程，為了迎合現今鋰電池的需求，輸入電壓設計在2.7伏至5伏。模擬結果可以極佳的穩壓在2伏，操作的負載電流範圍在極寬的範圍0.3毫安培至1000毫安培，輸出電壓的雜訊控制在8毫伏，而最高的效率則是達到百分之97.6。

The widespread demand of portable devices with imaging, multimedia, voice and data, has resulted in the requirement of efficiency power saving solutions to prolong battery life. The general converter modes are pulse width modulation (PWM) and pulse frequency modulation (PFM). But the efficiency of the PWM mode is low in light loading current and that of the PFM mode is low in heavy load. In order to maintain high efficiency, the dual-mode of PWM and PFM circuits have been presented. But these techniques usually didn’t find the best switching point. With the proposed buck converter, the technique to choose which mode can achieve high efficiency over wide loading range for improving the battery life. In order to increase the efficiency and decrease the area of the converter, dynamic partial shut down technique and combined PWM and PFM circuits are proposed. The converter is designed a 0.35um n-well CMOS process for a supply range of 2.7-5v which is compatible with state-of-the-art Li-ion batteries (2.7-5v).Simulation results show that the converter convert generates the output voltage of 2V while delivering up to 1000mA of load current with a maximum ripple of 8mV. An it’s maximum efficiency is 96.7%.

List of Contents
誌謝………..…………………………………………………… I
中文摘要…..………………………………………………….. II
Abstract………………………………………………………….. III
List of Contents……………………………………………….. V
List of Figures………………………………………………… VI
List of Tables………………………………………………………...... IIX
Chapter 1. Introduction……………………………………………... 1
1.1 Introduction…………………………………………........ 1
1.2 Organization of Thesis…………………....... 3
Chapter 2. Literature Survey……………………………... 4
2.1 Introduction……………………………………… 4
2.2 PWM…………….…….………………………… 4
2.3 PFM……………..……………………………….. 7
2.4 Combined PWM and PFM..................... 8
Chapter 3. Proposed Architecture……………..……….. 11
3.1 Introduction……………………………………… 11
3.2 The proposed Architecture……………….... 11
3.3 Dynamic partial shut down………………….... 12
3.4 Dead time buffer and zero current detection.14
3.5 Control……………………..………....…..…… 18
3.6 Vcons……………………..………………..……… 22
3.7 PFM……………………..………………..……… 23
3.8 PWM……………………………………………….. 29
3.9 Efficiency………………………………………... 31
Chapter 4. Simulation Results…………………………… 35
4.1 Introduction……………………………………… 35
4.2 Converter Performance ………………..…... 35
4.3 Summary……………………………………………… 42
Chapter 5. Conclusion..…………………………………… 43
References…………………………………………………….. 45

List of Figures
Fig. 1-1 Efficiency of the converter with two control modes......... 1
Fig. 2-1 The general PWM circuits…………………………. 5
Fig. 2-2 Waveforms of the Vc(t) compared with Vsaw(t). 6
Fig. 2-3 The general PFM circuits…….…………………. 7
Fig. 2-4 Waveforms of Qt(t)…………………………….... 8
Fig. 2-5 The simplified schematic of combined PWM and PFM mode circuits…………………………………………….. 9
Fig. 2-6 Phenomena of CCM and DCM………………...……. 10
Fig. 3-1 Block diagram of simplified proposed scheme….11
Fig. 3-2 Schematic of the ramp generator… 12
Fig. 3-3 Dynamic partial shut down circuit……...…… 14
Fig. 3-4 Schematic of the dead time buffer circuits… 15
Fig. 3-5 The relationship of inductance current and VPH1...................................................16
Fig. 3-6 The combined dead time buffer and zero current detection circuit……………………………………...…. 16
Fig. 3-7 Relationship delay of the combined dead time buffer and zero current detection……………………………17
Fig. 3-8 Circuit diagram of D flip-flop……………………18
Fig. 3-9 Schematic of counter and register……………… 19
Fig. 3-10 Theory of the counter.………………………..… 19
Fig. 3-11 Delay of the counter…………..…………………..20
Fig. 3-12 Way to solve the counter delay…………………..21
Fig. 3-13 The combined counter, register, and subtractor21
Fig. 3-14 Schematic of the PFM under dynamic partial shut down… 23
Fig. 3-15 Schematic of S’R’-latch and the performance…………... 24
Fig. 3-16 Performance of the output of the dead time buffer and
zero current detection in DCM………………………….. 25
Fig. 3-17 PFM operates in DCM…………………………………27
Fig. 3-18 PFM operates in CCM…………………………………27
Fig. 3-19 Control method of PFM………………………………28
Fig. 3-20 Schematic of PWM under dynamic partial shut down techniques……………………………………………….. 29
Fig. 3-21 Operation principle of PWM...………..……… 30
Fig. 3-22 The inductor current……………………………… 32
Fig. 3.23 Plot of the efficiency of the converter by MATLAB…… 34
Fig. 4-1 Start-up time of PFM………………………… 35
Fig. 4-2 Start-up time of PFM……………………………….36
Fig. 4-3 Voltage ripple of PFM…………………………... 37
Fig. 4-4 Voltage ripple of PWM………………………..……37
Fig. 4-5 Tracing time of the converter…………..………38
Fig. 4-6 The effect of the dead time buffer…………… 39
Fig. 4-7 The effect f the zero current detection………40

List of Tables
Table 4-1 Comparison of recent converters……………....41

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