臺灣博碩士論文加值系統

技術的演進，元件的尺寸被要求越來越小，相對難度也隨之提升。伴隨尺寸的縮小，超淺界面與低電阻的需求是元件的基石。傳統上使用較低的離子植入能量與較短時間的熱處理是形成淺界面有效方法。本論文提出利用載子共同植入的設計與釐米秒熱處理(millisecond annealing)的順序安排，來達成淺界面的需求，進一步驗證在元件上。
首先，我們研究離子佈植過程中形成的缺陷與載子的交互作用，透過缺陷的設計，加入碳載子共同植入，搭配傳統鍺、磷原子離子佈植與熱處理便能有效形成超淺界面，其超淺界面深度由原先46奈米變至20奈米。我們實驗上觀察到，鍺元素預非晶質化(preamorphization)深度的設計，扮演相當重要的角色。透過鍺元素預非晶質化與碳載子共同植入交互重疊，在熱處理的過程，有效隔絕離子佈植過程中形成的間隙原子(interstitial) ，進而形成超淺界面。其結果也與摩擬相吻合，此實驗論證能有效提供微小化元件設計的重要參考。
其次，我們提出碳載子共同植入技術應用在65奈米p通道元件上，透過硼原子有效的被阻隔而形成的淺界面，應用在金氧半場效電晶體源極/汲極的延伸區(source/drain extension)上。實繼於65奈米元件驗証上，可以達成26 mV (20%) DIBL元件特性改善。然而，我們亦可透過輕摻雜汲極(lightly doped drain)離子植入條件的重新設計，解決碳載子共同植入所形成陡峭界面引發高電場而形成漏電流加以改善。再者，我們提出新方法傾斜碳載子共同植入方法，應用於45奈米元件，可以達成5%元件驅動電流的增加，同時不僅避免離子佈植對矽鍺(SiGe)磊晶形成應力的破壞，同時有效改善矽鍺磊晶不平整表面所帶來金屬矽化物薄膜(NiSix)界面尖突(junction spiking)的問題，直達1-2 orders的減少。
最後，於此論文中，研究釐米秒熱處理與快速迴火較佳順序安排對於元件的引響。我們的結果顯示，釐米秒熱處理與快速迴火順序，對於元件扮演不同的節果。從控片上阻值相對改變量的分析，如果釐米秒熱處理在前而快速迴火在後，可增加固態溶解度多達18%之多，相較於快速迴火在前而釐米秒熱處理在後的情況。這樣的結論，亦反應在元件NMOS/PMOS相反變化的啟始電壓(threshold voltage)上。此熱迴火順序所帶來研究，能有效應用於超淺界面與縮小元件上。

As CMOS technology continue to scale down, dopant profile engineering has become one of the major technology challenged in CMOS device fabrication. In the aggressively scaled CMOS device, shallow p-n junctions and low sheet resistances are essential for short channel effect (SCE) control and high device performance. Conventionally, low-energy ion implantation and the spike anneal are utilized to form ultra shallow junction (USJ) in CMOS fabrication. This dissertation addresses the investigation of implantation damage induced anomalous diffusion by effective co-implant profile design and thermal sequence optimization of millisecond anneal which successfully demonstrates in scaled CMOS device. First, we have studied the interactions between implant defects and phosphorus diffusion in crystalline silicon. Defect engineering enables ultra shallow n+/p junction formation by using phosphorus, carbon and germanium co-implants, and spike anneal. The resultant phosphorus junction depth is less tan 20 nm comparing 46 nm without co-implants at phosphorus concentration of 5x1015 cm-3. Our experimental data suggest that the positioning of a preamorphized layer using germanium implants plays an important role in phosphorus diffusion. We find that extending the overlap of germanium preamorphization and carbon profiles results in greater reduction of phosphorus transient-enhanced diffusion (TED) by trapping more excess interstitials This conclusion is consistent with the end-of-range (EOR) defects calculated by Monte Carlos simulation and annealed carbon profiles. Our results also proved useful insight into the ultra shallow junction formation in aggressively scaled CMOS technology. Second, we present an alternative approach to achieve ultra shallow junction formation using carbon co-implant in the sub-65 nm PMOS devices in which the notorious boron interstitial diffusion is greatly retarded. Carbon co-implant is used in conjunction with boron implants in the source/drain extension (SDE) aiming at short channel effect improvement. Upon process optimization, 26 mV (20% improvement) drain induced barrier lowering (DIBL) improvement can be obtained. We also describe our efforts to circumvent the inevitable junction leakage during the co-implant process by source/drain extension implant profile re-engineering. Meanwhile, we present a new approach to achieve superior short channel effect control in the embedded SiGe p-MOSFET devices using tilted co-implant, in which resulting in greatly improved short channel effect and preventing implant induced strained relaxation problem. By this new approach, 5 % p-MOSFET Idsat improvement is demonstrated in sub-45nm node device. In addition, we demonstrate co-implant enhanced junction leakage current suppression by 1-2 orders of magnitude due to modifications of SiGe surface morphology in the presence of co-implant, where silicide spiking possibility during the silicidation process is greatly reduced, preventing junction leakage. Finally, we have studied the effects of the millisecond anneal in conjunction with conventional spike anneal on the p-n junction formation in CMOS devices. Our results reveal that the millisecond and spike anneal sequence plays an important role in the implanted boron p+/n junction formation. On blanket silicon wafers, the millisecond anneal followed by the spike anneal increases implanted boron solid solubility in crystalline silicon by ~18% compared to that obtained using reversed annealing sequence under the same annealing conditions. This result substantially alters the short channel effect behavior in the fabricated CMOS devices, resulting in opposite threshold voltage behaviors in PMOS and NMOS devices when using boron as NMOS halo implant. Our results also provide useful insights into ultra shallow junction formation and short channel effect control when scaling CMOS technology.

Contents
Abstract ……………………………………………………………II
摘要 …………………………………………………………………V
致謝……………. ………………………………………………… VII
Contents……………………………………………………………VIII
Table Captions………………………………………………………X
Figure Captions……………………………………………………XI

Chapter 1
Introduction____________________________________________1
1.1 Background and motivation …………………………………1
1.2 Objectives………………….. ……………………………….4
1.3 Organization of this dissertation …………..…………5

Chapter 2
Effects of Germanium and Carbon Co-implant on Phosphorus Diffusion in Silicon____________________________________10
2.1 Introduction……………………………..……………………10
2.2 Device fabrication…………………………………… ……11
2.3 Results and discussions…………..………….……………12
2.3.1 Mechanism of dopant retardation
2.3.2 Simulation of dopants distribution
2.4 Summary…………………………………..……………………15

Chapter 3
Ultra-Shallow Junction Formation Using Co-implantation for PMOS Short Channel Effect Improvement in 65 nm Technology and Beyond _____________________________________________23
3.1 Introduction………………………………..…………………23
3.2 Device fabrication………………………………………………….…… 24
3.3 Results and discussions…………………… ……….……24
3.3.1 Device characteristics
3.3.2 Poly depletion and junction leakage
3.4 Summary…………………………………..……………………26

Chapter 4
Short Channel Effect Control in Aggressively Scaled Strained P-MOSFETs Using Tilted Co-implant for Front-End-of-Line (FEOL) 45 nm Technology and Beyond__________________________________________________36
4.1 Introduction……………………………………………………36
4.2 Device fabrication……………………………….…………37
4.3 Results and discussions…………………………………………………………37
4.3.1 Device optimization
4.3.2 Junction leakage benefits
4.4 Summary ………………………………………………………41

Chapter 5
Millisecond Anneal and Short Channel Effect Control in Si CMOS Transistor Performance ___________________________60
5.1 Introduction……………………………………………………60
5.2 Experiments……………………………………………………61
5.2.1 Device fabrication
5.2.2 Process for comparison
5.3 Results and discussions …………………………………62
5.3.1 Thermal sequence comparison results
5.3.2 Device characteristics
5.4 Summary ………………………………………………………65

Chapter 6
Conclusions ____________________________________________71
6.1 Conclusions ……………………………………………………71

Reference_______________________________________________74
Publication List _______________________________________83

Reference

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