臺灣博碩士論文加值系統

SSD是使用NAND Flash Memory來當作儲存元件，它具有抗震、讀取速度快等特性。SSD為了加快它讀寫的速度，都會採用multi-channel的架構，而SSD的容量逐漸增加，內部的flash chips也越來越多，使得一個request的size沒有辦法讓所有的flash chips工作，造成有些chips處於idle狀態。Device一次只能接受一個request讀取，而且OS對於sequential read access都會分為好幾個requests下給device，所以我們提出一個prefetch的方法，用來預測sequential read access，希望把這些sequential read requests連接起來，這麼一來可以加速SSD處理sequential read access的速度。然後我們還在不同的硬體架構下，觀察prefetch所造成的影響。最後實驗結果顯示，我們的prefetch方法在8-channel的SSD以及每個channel裡有4個flash chips的架構下，可以改善約22.5%的效能。

The storage component of SSD is NAND flash memory, it has shock resistance and high speed of read operation. SSD uses multi-channel architecture for increasing speed of read/write operation. Therefore the storage size of SSD and flash chips in it is increasing such that a request does not cause all chips to work, and some chips are idle. A device can service up to one request at a time, and OS separates the sequential read access to many requests to command the device. We proposed a prefetch policy for predicting sequential read access, and hoped to connect the sequential read requests. By this way it could speed up the progress of sequential read access on SSD. Then we also observe the effect of prefetch on different hardware architectures. Finally, our prefetch policy used on the SSD architecture with 8-channel and four flash chips in each channel can improve about 22.5%.

目錄
中文摘要 i
英文摘要 ii
目錄 iii
表目錄 iv
圖目錄 v
一、 Introduction 1
二、 Background 3
2.1 Flash memory characteristics 3
2.2 Multi-channel and interleaving 4
2.3 Motivation 5
2.4 Related work 6
三、 Adaptive Prefetch for Multi-channel SSD 8
3.1 Overall hardware architecture 8
3.2 Prefetch policy 10
3.3 Thread identification 13
3.4 Buffer replacement 15
四、 Experimental result 15
4.1 Experimental setup and performance metrics 15
4.2 Read ahead size 17
4.3 Prefetch buffer size and replacement 20
4.4 Number of channels 22
4.5 Interleaving degree 23
五、 Conclusion 24
References 26

參考文獻
1. Jeong-Uk Kang, Jin-Soo Kim, Chanik Park, Hyoungjun Park, Joonwon Lee, "A multi-channel architecture for high-performance NAND ?ash-based storage system" ,Received 9 December 2005; received in revised form 5 January 2007; accepted 8 January 2007;Available online 1 February 2007
2. Li-Pin Chang, Tei-Wei Kuo, "An Adaptive Striping Architecture for Flash Memory Storage Systems of Embedded Systems," The 8th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2002) September 24 -27, 2002. San Jose, California.
3. Nitin Agrawal, Vijayan Prabhakaran, Ted Wobber, John D. Davis, Mark Manasse, Rina Panigrahy , " Design Tradeoffs for SSD Performance", USENIX '08 Refereed Paper Pp. 57–70 of the Proceedings.
4. Samsung Elec. 2Gx8 Bit NAND Flash Memory (K9WAG08U1A). 2006.
5. Samsung Elec. 2Gx8 Bit NAND Flash Memory (K9GAG08U0M-P).2006.
6. Cagdas Dirik, Bruce Jacob, " The performance of PC solid-state disks (SSDs) as a function of bandwidth, concurrency, device architecture, and system organization ", Proceedings of the 36th annual international symposium on Computer architecture ,@ 978-1-60558-526-0, Austin, TX, USA, 279-289, 2009, http://doi.acm.org/10.1145/1555754.1555790, ACM
7. Jacob, B., Ng, S., and Wang, D. 2007. Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann.