臺灣博碩士論文加值系統

對於一個系統晶片，若要完全利用其中的矽智財就必須針對系統層作最佳化．系統層的最佳化意味著盡量降低更改矽智財的需要，且同時提高其矽智財間的溝通效率．本篇論文呈現在一個H.264/AVC影像解碼器系統晶片所作的的系統層分析與最佳化． 四種最佳化方式，其中包括了兩種降低DRAM存取處罰的方式與兩種降低系統閒置時間的方式，同時使用時可減少執行時間達12.3%，增加 DRAM在仲裁交接時的row-hit量達243%，且降低系統閒置時間達84%．另外，為了支援有及時需求的匯流排主控模組，本篇論文採用了先前所開發之ＷＢＡ仲裁演算法．本論文中所提出的方法，技巧，矽智財設計，以及最佳化解碼器晶片時的導論，都可採用於其他有匯流排的系統晶片上．

In a System-on-Chip (SoC), to fully utilize IPs require system-level optimization. System-level optimization implies minimum modifications on the IPs while boosting the communication efficiency. This paper demonstrates the process and result of a system-level analysis and optimization on an H.264/AVC video decoder SoC. Four optimization approaches, including two that minimize DRAM access penalty and two that minimize system idle time, together reduce total execution cycles (i.e. total bus cycles) by up to 12.3%, increase DRAM row-hits on bus-grant handover by up to 242%, and decrease system idle cycles by up to 84% on decoding B frames. This paper also adopts the Warning-line Based Algorithm (WBA) to support Real-Time (RT) bus masters. All proposed methodologies, techniques, IP designs, as well as reasoning involved in optimizing this video decoder intend to be applicable also on other bus-enabled SoCs.

Abstract i
Table of Contents ii
List of Figures iv
List of Tables vi
Chapter 1 Introduction 1
Chapter 2 Preface on DRAM and System Performance 4
2.1 DRAM Access Penalties 4
2.2 DRAM Controller Design 6
2.3 Measuring System Performance on Bus 7
Chapter 3 Related Works 10
3.1 Sub-IP Memory-mapping Design 10
3.2 Memory Controller Design 12
3.3 Bus Arbitration Design 14
Chapter 4 Environmental Assumptions 16
4.1 System-level Assumptions 16
4.2 Bus-level Assumptions 16
4.3 Sub-IP-level Assumptions 17
Chapter 5 Qualitative Analysis of the NTHU H.264 Video Decoder 19
5.1 System Environment 19
5.2 System Throughput Requirements 21
5.3 DRAM Access Behavior 22
5.4 Internal Arbitration Scheme 24
Chapter 6 Quantitative Analysis of the NTHU H.264 Video Decoder 25
6.1 System Performance Analyzer (SPA) 25
6.2 Analyzer Report Walkthrough 27
6.3 Key Observations 32
Chapter 7 Proposed Optimization Approach 34
7.1 Optimization for DRAM Accesses 34
7.2 Optimization for Master Sub-IPs 36
7.3 Real-Time Considerations 38
7.4 Candidate Filtering Mechanism (CFM) 39

Chapter 8 Proposed DRAM Controller 42
8.1 Features 42
8.2 DRAM Module Specification 43
8.3 Architectural Description 44
8.4 Standby Transfer Handling (STH) 47
Chapter 9 Simulations 49
9.1 Environmental Description 49
9.2 Procedures 50
9.3 Results without BFMs 51
9.4 Results with BFMs 53
9.5 Result Analysis 54
Chapter 10 Conclusion and Remarks 56
Bibliography 57
Appendix 1: Part I Simulation Results 59
Appendix 2: Part II Simulation Results 60

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