臺灣博碩士論文加值系統

偏移誤差校正技術可以偵測偏移誤差電壓的量並且調整電路來消除偏移誤差，但是前景式偏移誤差校正技術只會校正一次，這樣是很難校正由溫度和供應電壓的變化所造成的偏移誤差的變化。在這篇論文提出一個偏移誤差校正電路使前置放大器和比較栓鎖器的電路能夠匹配，這意指前置放大器和比較栓所器的偏移誤差會被校正。因為此偏移誤差校正電路是由開關-電容所組成的電路，耗費的功率是比較少，而且此電路不會放在運作比較的電路交接處，因此不會影響比較的操作速度。再搭配一個新的開關網路系統，將可以實現一個背景式偏移誤差校正技術來避免偏移誤差的變化量。

此快閃式類比數位轉換器之實現是採用TSMC 0.13微米，1P8M互補型金氧半混合信號製程，模擬經過校正功能後，在1GHz的取樣頻率下，輸入訊號為480MHz時，此類比數位轉換器有36分貝的SNDR動態表現。整個晶片不包含輸出緩衝器共消耗了13.2mW的功率，FoM是259f焦耳。而大部分可以設計出來的類比數位轉換器FoM大約在0.5p到10p焦耳。

Offset calibration is a technique which detects the offset and adjusts the circuit configuration accordingly. However, foreground calibration only processes once which is not easy to prevent offset variations caused by temperature and supply voltage. In this thesis, the offset calibration circuit is proposed to make the circuit of the preamplifier and the comparator-latch match. It means that the offset voltages of the preamplifier and the comparator-latch are calibrated. Since the offset calibration circuit is based on the switch-capacitor circuit, the requirement of the power is less. The switch-capacitor circuit does not located at the connection of the conversion circuits, which does not affect the operating rate of the conversion. With the new switch network, the background offset calibration technique is implemented to prevent the offset variation.

A 6-bit 1GSample/s flash ADC is implemented by TSMC 0.13um 1P8M CMOS process. After calibration, the simulation results show that SNDR is 36dB with 480MHz input frequency at 1GHz sample rate. The power consumption is 13.2mW where output buffers are not included. FoM of this ADC is 259fJ/conversion-step. Other comparable designs have FOMs between 0.5 to 10 pJ.

1 Introduction………............................................................. 1
1.1 Motivation................................................................................................... 1
1.2 Organization…............................................................................................ 2

2 Overview of High-Speed ADC............................................ 4
2.1 Flash A/D Converter................................................................................... 4
2.2 Two-step Subrange A/D Converter............................................................. 6
2.3 Folding A/D Converter…………………………………………………... 8
2.4 Pipeline A/D Converter…………………………………………………... 9
2.5 Interleaved A/D Converter………………………………………………. 10

3 Error Analysis of Flash ADC …………………………...... 12
3.1 Quantization Error..…………..................................................................... 12
3.2 Noise……………………........................................................................... 15
3.3 Offset Mismatch......................................................................................... 17
3.4 Clock Skew Effect………………….......................................................... 21
3.5 Signal Dependent Comparator Delay Error…............................................ 24
3.6 Metastability and Hysteresis...................................................................... 28
3.7 Jitter……………………….……….…...................................................... 31

4 Proposed Technique for the Flash ADC……….................. 33
4.1 Auto-zeroing Technique...…....................................................................... 33
4.1.1 Auto-zeroing Principle….............................................................. 34
4.1.2 Auto-zeroing Topology.................................................................. 35
4.2 Averaging Technique….............................................................................. 37
4.2.1 Resister Averaging Network.......................................................... 37
4.2.2 Offset Reduction with Averaging Network................................... 40
4.3 Proposed Offset Calibration Circuit........................................................... 42

5 Circuit Design of the Flash ADC......................................... 48
5.1 The Architecture of Proposed ADC............................................................ 48
5.2 Reference Ladder Consideration…............................................................ 49
5.2.1 Effect to the Accuracy of Resistor Ladder..................................... 49
5.2.2 Matching Behavior of the Resistor Ladder................................... 50
5.2.3 Input Feedthrough of the Resistor Ladder………………………. 51
5.3 Comparator Circuit Design…..................................................................... 52
5.3.1 Circuit Topology and Consideration............................................. 52
5.3.2 Preamplifier Circuit…................................................................... 53
5.3.3 Latch Circuit………...................................................................... 54
5.4 The Proposed Background Calibration Technique…................................. 55
5.5 Digital Encoder Design…………………………………………………... 60
5.5.1 Consideration of Digital Encoder.................................................. 60
5.5.2 Implementation of Digital Encoder............................................... 61
5.6 Timing Generator Circuit............................................................................ 62

6 Layout and Results.............................................................. 65
6.1 Power Supply Partition............................................................................... 65
6.2 Floor Plan and Layout................................................................................. 66
6.3 Simulation Result………………………………………………………… 67
6.4 Measurement Considerations….................................................................. 71
6.4.1 Measure Setup............................................................................... 71
6.5 Considerations of the PCB Design…......................................................... 72
6.5.1 Transmission Line Effect.............................................................. 72
6.5.2 Crosstalk........................................................................................ 73
6.5.3 Decoupling.................................................................................... 73
6.5.4 PCB Fabrication............................................................................ 73

7 Conclusion and Future Work............................................... 75

Reference 77

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