臺灣博碩士論文加值系統

今日的功率放大器大多以GaAs、HBT、LDMOS、BiCMOS…等來實現，然而，有越來越多的通訊系統都以CMOS來製作，基於這樣的理由，使得單一晶片CMOS傳收機的需求漸增。因此，在本篇論文中即是描述一個功率放大器電路的設計與實現。
然而，在實現CMOS功率放大器時遭遇許多CMOS本身的缺點，因此我們必須使用不同的方式，以取代傳統上使用GaAs或是BJT的方法。而我們所使用的是TSMC 0.25 m的製程，並且使用開關式E類放大器的架構以求達到較高的效率。此外，還使用在一般MOS汲極端非線性的陡接面寄生電壓電容特性來取代線性的電容，並提出全差動型式的架構來解決CMOS本身的問題。最後，再設計一個低損耗且相差180 相角以微帶線製程的混成器。
以16dBm輸入混成器，得模擬的輸出功率是20.48dBm，效率是30%。但實際量測上，由於電路的佈局，因此與模擬結果有差異，將在後面章節做說明。

Today’s power amplifiers are implemented in GaAs, HBT, LDMOS, and BiCMOS technologies. However, more and more communication system is fabricated in CMOS technology. For this reason, a single chip transceiver includes an integrated CMOS power amplifier. In this work, design and implementation of a power amplifier are described.
However, the implementation of a CMOS power amplifier suffers from many disadvantages of intrinsic CMOS characteristics. Therefore, we have to introduce a different approach from the standard way which is used to design GaAs or bipolar power amplifier. We use TSMC 0.25 m processes with a switching Class E approach, which can achieve high efficiency. And we use a nonlinearly parasitic capacitance with hyperabrupt junction capacitance characteristics instead of linear one at the drain-to -bulk junction of practical MOS devices. A fully differential topologies are presented the problems of CMOS technology. In addition, a low insertion, 180 hybrid is implemented with microstrip line.
In the simulation results, we obtain the output power is 20.48 dBm, and the efficiency is 30% with input power of 16dBm.Because of some implement errors, the measurement results have some mismatch and will be illustrated.

指導教授推薦書………………………………………………………
口試委員會審定書……………………………………………………
授權書……………………………………………………………….... iii
誌謝………………………………………………………………….... iv
中文摘要…………………………………………………………….... v
英文摘要…………………………………………………………….... vi
第一章 緒論…………………………………………………………... 1
1.1 研究動機…………………………………………………… 1
1.2 研究背景…………………………………………………… 2
1.3 研究方法與步驟…………………………………………… 3
1.4 章節簡介…………………………………………………… 4
第二章 E類功率放大器……………………………………………… 6
2.1 簡介………………………………………………………… 7
2.1.1 功率放大器……………………………………………. 7
2.1.2 電路架構………………………………………………. 9
2.2 規格………………................................................................ 10
2.2.1 效率…………...………………………………………. 10
2.2.2 功率增益…………….……………………………….... 11
2.2.3 穩定度…………………………………………………. 13
2.2.4 1-dB 壓縮點…………………………….…………….. 16
2.3 功率放大器………………………………………………… 17
2.3.1 線性功率放大器………………………………………. 17
2.3.2 開關式功率放大器…………………………….……… 18
2.4 E類功率放大器特性……………………………………. 19
2.4.1 100%的效率…………………………………………... 20
2.4.2 電晶體的低損耗………………………………………. 21
2.4.3 作用在三極體區和截止區………………………….... 22
2.4.4 寬頻…………………………………………………..... 23
2.4.5 功率的可控制性………………………………………. 23
2.5 E類功率放大器……………………………………………. 24
2.5.1 E類功率放大器的架構…………………………….. 24
2.5.2 E類功率放大器的作用原理……………………….. 25
第三章 功率放大器的設計…………………………………………... 32
3.1 CMOS元件的特性…………………………………………. 32
3.1.1 低電流負載能力………………………………………. 33
3.1.2 低崩潰電壓…………………………………………..... 34
3.1.3 大寄生電容…………………………………………..... 34
3.1.4 基底雜訊………………..……………………………... 36
3.2 設計的架構………………………………………………… 36
3.2.1 模型……………………………………………………. 36
3.2.2 E類功率放大器……….………………………………. 38
3.2.3 汲極端的電容………..………………………………... 38
3.2.4 電路架構………………………………………………. 40
3.2.5 差動式的架構…………………………………………. 42
3.3 模擬結果…………………………………………………… 43
3.3.1 單端Class E功率放大器……………………………… 44
3.3.2 差動式功率放大器……………………………………. 49
3.4 180 混成器……….………………………………………... 52
3.4.1 混成器…………………………………………………. 52
3.4.2 環狀混成器……….…………………………………… 53
3.4.3 總體混成器… ……………………………………….... 57
3.4.4 討論……………………………………………………. 60
第四章 功率放大器的製作…………………………………………... 61
4.1 佈局考量………………………………………………….... 61
4.1.1 螺旋型電感的實現……………………………………. 62
4.1.2 焊線……………………………………………………. 64
4.1.3 電流密度……………………………………………. 65
4.2 佈局………………………………………………………… 66
4.2.1 電路佈局………………………………………………. 66
4.3 量測………………………………………………………… 68
4.3.1 量測架構………………………………………………. 69
4.3.2 電路量測………………………………………………. 71
4.3.3 混成器量測……………………………………………. 78
4.3.4 討論……………………………………………………. 81
第五章 結論及未來工作……………………………………………... 82
5.1 結論……………..………………………………………….. 82
5.2 未來工作……………..…………………………………….. 83
參考文獻……………………………………………………………… 84
附表A…………………………………………………………………. 88
附表B…………………………………………………………………. 91
附表C…………………………………………………………………. 92

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