臺灣博碩士論文加值系統

競爭激烈的市場對於電子產品的需求趨向多功能、體積小、重量輕的終端產品。高功能密度之需求促使電子元件I/O(Input/Output Terminal)間距日趨減小，此將影響印刷電路板組裝製程之IC(Integrated Circuit)元件置放良率。然而，影響元件組裝良率之各製程參數，常需要使用實驗設計方法，決定實驗因子以及水準，以求得最佳製程參數，但實驗設計卻往往受限於樣本數不足，以致於難以推估實際生產良率。此外，影響產品良率的因素眾多，若能有效的預估組裝良率，業者在設計初期即可確保組裝良率。
本研究期望針對目前手持式產品市場主流之堆疊式封裝元件(Package on Package, PoP)，晶片等級封裝元件(Chip Scale Package, CSP)，元件分析其組裝製程，考量元件相關變異、錫膏/助銲膏厚度的變異、元件及基板曲翹的影響，以及PoP/CSP錫球高度的變異等因素，運用蒙特卡羅模擬法，預測非平面Z方向是否發生空銲現象。研究針對邁威爾科技(Marvell)及海力士半導體(Hynix)所開發之PoP元件，分析其置放良率並應用蒙地卡羅模擬法建立模型以進行預測，以確保並提升良率，模擬結果發現，採用最佳製程參數組合之底層組裝良率為99.97%以及頂層組裝良率為86.76%，研究成果可供半導體封裝廠及系統組裝廠在生產新陣列構裝元件前，以模擬的方式預估生產品良率，可作為合作廠商導入PoP製程之參考。

The market demand has driven the electronic products toward the increased functionality and end product size/weight miniaturation. The above mentioned requirements significantly reduce the I/Os pitch. This would impact the assembly/packaging process yield of the devices. The design of experiments is typically used to determine the desired process parameters and resulted assembly yield. However, there are several factors involved and samples are sometime limited for conducting the experimentation. Therefore, effectively determine the influence of critical factors and predict the process yield are essential in the industry.

This research analyzes the assembly process parameters, component variations, component and board warpage. The Package on Package (PoP) are under consideration. Monte Carlo simulation technique was used to predict the assembly yield. This research analysis the PoP chip set developed by Marvell/Hynix.
Base on simulation result, the dominant factors influencing assembly yield is componrnt/PCB warpage and prccess/material selection. The research helps determine desired package design and assembly process to minimize the risk of PoP assembly yield loss.

目錄
摘要 I
Abstract II
目錄 III
表目錄 VI
圖目錄 VII
第一章　緒論 1
1.1　研究背景 1
1.2 研究動機 1
1.3　研究目的 2
1.4　研究架構與限制 3
第二章　文獻探討 5
2.1 立體堆疊元件組裝相關文獻回顧 5
2.2 印刷電路板曲翹以及元件曲翹相關文獻 9
2.3蒙地卡羅模擬相關文獻回顧 10
第三章　研究方法 12
3.1 蒙特卡羅模擬法 12
3.2 隨機數產生法 13
3.3模擬抽樣次數 16
3.4 研究的範圍與限制 17
第四章 堆疊式封裝元件組裝製程 19
4.1 表面黏著技術組裝製程 19
4.1.1 錫膏印刷 19
4.1.2 元件置放 21
4.1.3 熔焊 23
4.2堆疊式黏著技術組裝製程 25
4.2.1 3D封裝製程 25
4.2.1 PoP堆疊製程 26
第五章 立體堆疊銲點空銲公式之建立 31
5.1 影響銲點空銲因素分析 31
5.1.1 錫球高度 31
5.1.2 錫膏高度 33
5.1.3 電路板以及元件曲翹造成的高度差 34
5.2 空銲模式一基本假設 39
5.3 參數定義 40
5.4 建構模式一 42
5.5 建構模式二 47
第六章 推疊式元件組裝良率預測 51
6.1 選定實驗因子水準 51
6.2 組裝良率預測程式 52
6.3 高溫迴銲對PoP元件組裝良率影響 59
6.4 組裝性實驗模擬結果 62
6.5 錫球標準差對PoP元件組裝良率影響 64
6.6初步結論 66
第七章　結論 68
7.1　結論與建議 68
7.2 研究貢獻/ 69
7.3　未來展望與後續研究建議 70
參考文獻 71
一、　英文文獻 71
二、　中文文獻 73

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