|
[1] A. A. Abidi, “High frequency noise measurements on FET’s with small dimensions,” IEEE Trans. Electron. Devices, vol. 33, pp. 1801–1805, Nov. 1986. [2] C. M. Hung and K. K. O, “A Packaged 1.1GHz CMOS VCO with Phase Noise of –126dBc/Hz at a 600kHz Offset,” IEEE J. Solid-State Circuits, vol. 35, pp. 100–103, Jan. 2000. [3] S. T. Lee, S. J. Fang et al., “A quad-band GSM-GPRS transmitter with digital auto-calibration,” IEEE J. Solid-State Circuits, vol. 39, pp. 2200–2214, Dec. 2004. [4] C.-M. Hung, N. Barton, M.-C. Lee, and D. Leipold, “An ultra low phase noise GSM local oscillator in a 0.09-μm standard digital CMOS process with no high-Q inductors,” in Proc. IEEE Radio Frequency Integrated Circuits (RFIC) Symp., pp. 483–486, Jun. 2004 [5] 3GPP Technical specification 05.05 v 8.20.0, European Telecommunications Standards Institute (ETSI). [6] C. P. Yue and S. S. Wong, “On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC’s.” IEEE J. Solid-State Circuits, vol. 33, pp. 743–752, May. 1998. [7] Y. P. Tsividis and K. Suyama, “MOSFET modeling for analog circuit CAD: Problems and prospects,” IEEE J. Solid-State Circuits, vol. 29, pp. 210–216, Mar. 1994.
[8] A. Hajimiri and T. H. Lee, “Oscillator phase noise: a tutorial, ” IEEE J. Solid-State Circuits, vol. 35, no. 3, pp 326-336, Mar. 2000 [9] D. B. Lesson, “A simple model of feedback oscillator noise spectrum,” Proc. IEEE, vol. 54, no. 2, pp. 329-330, Feb. 1966. [10] T.Y. Lin, T.Y. Yu, L.W Ke, G.K Dehng, “A low-noise VCO with a constant KVCO for GSM/GPRS/EDGE applications,” IEEE Radio Frequency Integrated Circuits (RFIC) Symp., pp. 387–390 Jun. 2008 [11] Behzad Razavi, “RF Microelectronics,” Upper Saddle River, NJ: Prentice Hall. 1998, pp. 227–228 [12] E. Hegazi, H. Sjoland, and A. A. Abidi, “A filtering technique to lower LC oscillator phase noise,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1921-1930, Dec. 2001 [13] Gupta, A.S. Nava, J.F.G. Walls, F.L. “A novel low noise regenerative divide-by-four circuit,“ IEEE International Frequency Control Symposium and PDA Exhibition, pp. 680-684, 2002. [14] S. Levantino, L. Romano, S. Pellerano, C. Samori, A.L. Lacaita, “Phase noise in digital frequency dividers,” IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 775-784, May. 2004. [15] D. E. Phillips, “Random noise in digital gates and dividers,” in Proc. 41st Annu. Freq. Contr. Symp., IEEE, 1987, pp. 507-511 [16] Clock (CLK) Jitter and Phase Noise Conversion, Application Note 3359, MAXIM. [17] Y. Ji-Ren, I. Karlsson, and C. Svensson, “A true single-phase-clock dynamic CMOS circuit technique,” IEEE J. Solid-state Circuit, vol. 22, no. 5, pp. 899-901, Oct. 1987. [18] H. Darabi and A. A. Abidi, “Noise in RF-CMOS mixers: a simple physical model,” IEEE J. Solid-State Circuits, vol. 35, no. 1, pp. 15–25, Jan. 2000. [19] C.G. Huang, “Implementation of true single-phase clock D flipflops,” Electronics Letters, vol. 30, no. 17, pp1373-1374, Aug. 1994. [20] A.M. Gomez, J. Navarro, “Implementation of a programmable high speed divider for 2.4GHz CMOS integer-N frequency synthesizer,” X Workshop IBERCHIP, Oct.~Dec./2004.
|