臺灣博碩士論文加值系統

在晶片設計中，記憶體負責儲存資料並提供處理模組使用，而記憶體存取的時間會顯著影響系統整體效能。在本研究中，我們實作出一個基本記憶模組的可構形結構與設計組成，包括記憶介面、記憶控制器、記憶陣列、列緩衝器、列解碼器與行解碼器，以探討不同記憶體模組的設計。運用此可構形結構可有效縮減設計時程並提昇記憶存取效能。我們並透過SystemC程式語言實作這些組成功能並進行可構形實驗。

In system-on-chip designs, memory designs store data to be accessed by processing modules. Memory access time can affect overall system performance significantly. In this research, we implemented a configurable architecture of a basic memory module and its design composition, including memory interface, memory controller, memory array, row buffer, row decoder and column decoder. We explore various memory module designs. Utilizing the configurable architecture, we can effectively reduce design time and improve access time of memory module designs. We also realized these functionalities in SystemC language and performed configurability experiments.

第一章 緒論.1
1.1 研究動機.1
1.2 研究背景.2
1.3 問題敍述.3
1.4 論文架構.4
第二章 基本記憶模組功能的階層式結構.5
2.1記憶模組的基本功能結構5
2.2記憶介面功能結構7
2.3記憶控制功能結構9
2.3.1運算控制.9
2.3.2主要控制.10
2.4記憶陣列功能結構12
2.5列緩衝區功能結構16
2.6重新功能結構17
第三章 記憶模組進階功能的軟體規劃.19
3.1軟體設計規劃19
3.1.1 使用工具介紹19
3.1.2 設計規劃21
3.2記憶介面功能結構軟體設計22
3.3記憶控制功能結構軟體設計24
3.4記憶陣列功能結構軟體設計25
3.5列緩衝區功能結構軟體設計26
3.6重新功能結構軟體設計27
第四章 結論.28
參考文獻.29

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