臺灣博碩士論文加值系統

近年來可攜式即時腦波系統已經成為生醫電子領域發展的重點，且已被廣泛的運用在醫療、生物醫學和腦認知科學領域上。如腦機介面系統的應用，使人們可以運用大腦直接與機器電腦溝通，進一步得到幫助。由於生理電信號中最微弱的腦電信號通常與肌電信號(EMG)中的眼動信號與眨眼信號一起混合並量測，這些雜訊會影響即時腦波系統應用的處理和計算。獨立成分分析被證明為有效的人工雜訊濾除技術且發展許久。但由於獨立成份分析的運算複雜度過高，腦波的應用端通常受到離線運算的嚴重限制。
線上遞迴獨立成份分析演算法 (ORICA) 被證實能進行有效的線上獨立成分分離，本論文針對應用於可攜式即時腦波系統，設計與實現高效率的多通道線上遞迴獨立成份分析處理晶片。由於可攜式儀器的基本需求即為低功率與低成本，多種設計技巧與最佳化規格分析如鏡像非線性查表單元與有效的ORICA訓練單元的設計、各計算單元間的管線排程與自動學習率機制皆被用來達成線上處理和降低功率消耗與硬體成本。此ORICA硬體設計已被整合至基於線上遞迴式獨立成分分析以及肌電雜訊自動去除機制之多通道腦波擷取系統晶片。此系統晶片設計由台積電90奈米製程下線。晶片的核心面積為1.44平方毫米。使用128 Hz的取樣頻率，晶片操作於50 MHz的工作頻率與1.0 V的核心電壓時，功率消耗為2.859毫瓦，並利用國家晶片中心提供的Agilent 93000 測試機台完成功能性測試。
此多通道腦波擷取系統晶片整合了前端晶片控制模組、高效率多通道線上遞迴獨立成份分析處理器、自動肌電雜訊去除機制和後端藍芽傳輸介面。生醫訊號由前端訊號擷取模組取得並傳送至獨立成份分析處理器進行獨立成份分離。自動肌電雜訊去除機制將自動判別肌電雜訊，並進一步進行雜訊去除且還原乾淨的腦電訊號，處理完的結果與原始訊號皆由一商業藍牙模組以無線方式傳至臨近的生醫資訊工作站或可攜式行動裝置進行顯像與遠端觀察與診斷。獨立成份分析引擎皆以真實生理訊號驗證，並顯示優良的分析結果。此低成本、低功耗的晶片實現提供了有效的腦波雜訊和成分分離，且完成自動雜訊消除與重建乾淨的腦波成份，使得可攜式即時腦波系統的應用能夠得到更高準確度的重要腦波信息並提供相關應用即時性的分析處理。

Electroencephalogram (EEG) is a noninvasive tool for measuring the electrical activity in the brain, and to date has found many useful applications in the medical, consumer and entertainment industries. Since the EEG is the feeblest one of all physiological electrical signals usually contaminated by ocular artifacts (e.g. Eye-blink artifact and eye-movement artifact), the artifact removal techniques using independent component analysis (ICA) has been developed for a long time. Because of the compelling computation complexity of the ICA algorithm directly inherits from the possible dependency in each channel, applications that analyze EEG signals are usually heavily restricted by the off-line ICA computation. To achieve on-line ICA processing, the online recursive ICA algorithm is proposed, which has a fast convergence rate and a good steady state performance. Since real- time EEG systems, such as BCI with ICA computation is demanded to control an external device on-line and to monitor the biomedical signals, the low computation time is desired. On the other hand, due to the energy limitation of a portable device, the low-energy system is expected. In order to support the portable demand and achieve the on-line feedback, a low-energy and low computation-time ICA implementation is required.
This thesis proposes a high-efficient chip implementation of multi-channel on-line recursive independent component analysis processor for portable real-time EEG systems. It uses both the low-power system-on-chip (SoC) technology and the effective system integration techniques to achieve a highly miniaturized low-power ORICA processor. The proposed design uses hardware parallelism and pipeline to achieve real-time processing and data handling. The proposed design also uses time-multiplexed design concept to fully use sharable hardware resources, parallel multipliers and adders, and a 256X32 bits memory. Moreover, the high efficiency ORICA weight training unit (ORICAWTU) with various design techniques like a kurtosis size decision, an optimized mirrored non-linear lookup unit and an automatic learning rate decision procedure and optimized specification analyses is designed to efficiently estimate unmixing weight. Therefore, hardware cost and power consumption can be narrowed down. All the computing engines adopt a hybrid format with fixed point and floating point to ensure the high accuracy during operation processing. The proposed ORICA processor is employed and integrated in the online recursive ICA based real-time multi-channel EEG acquisition system on chip design with automatic eye blink artifact rejection. The EEG acquisition system on chip design is fabricated using TSMC 90nm CMOS technology. The chip gate count, core area and operating frequency of the proposed ORICA processor are 0.269 million, 1200 x 1200 μm2 and up to 50MHz, respectively. The performance and processing results of the proposed design are also shown to reach 0.0078125 s latency after each EEG sample time. The chip is tested by Agilent 9300 and the power consumption is 2.859mW.
The super-Gaussian random signals, the sub-Gaussian random signals and real EEG signals are applied to evaluate the performance of the designed processor. The proposed design can effectively separate the EEG signals. The average correlation coefficient between the random source signals and extracted ORICA signals for each 1s frame is over to 0.9. In real EEG separation, the result shows that the component of eye blink artifacts is exactly separated from the raw EEG signal, and component correlation between the on-line result and the off-line result achieves 0.9956. Although the performance of EEG signal with electrical noises is not really good, the electrical noises components are still separated from EEG signal. Over 0.85 average correlations between off-line result and the on-line processing using real EEG signals which contain electrical noises or eye-blink artifacts or stable without eye-blink artifacts is also demonstrated.
Finally, a portable real-time EEG system based on the EEG acquisition system on chip design with automatic eye blink artifact rejection is also implemented. It comprises an 8 channel electrodes for EEG signal acquisition, the self-made PCB contained the proposed Chip, an ADS1298 chip, and the Bluetooth for signal processing and wireless transmission, and the friendly user interface based on the Android platform. It reduces the complexity of EEG system and provide a more accurate EEG information extraction to various EEG systems in real-time.

中文摘要 I
ABSTRACT III
誌謝 VI
CONTENT VII
LIST OF FIGURES IX
LIST OF TABLES XIII
CHAPTER 1 INTRODUCTION 1
1.1 ELECTROENCEPHALOGRAPHY 1
1.2 THE MOTIVATIONS FOR AN CHIP IMPLEMENTATION OF ORICA PROCESSOR 6
1.3 THE CONTRIBUTION OF THIS WORK 8
1.4 APPLICATION SCENARIOS 10
1.4.1 Real-time Observation and Monitoring 10
1.4.2 Research on Brain and Cognitive Science 11
1.5 ORGANIZATION OF THE THESIS 12
CHAPTER 2 THEORETICAL BACKGROUND 14
2.1 BLIND SOURCE SEPARATION 14
2.2 ONLINE RECURSIVE INDEPENDENT COMPONENT ANALYSIS 16
2.3 THE OPERATION FLOW OF THE PROPOSED ORICA PROCESSOR 20
2.3.1 Whitening 20
2.3.2 Operation flow of ORICA processing 21
CHAPTER 3 8-CHANNEL INDEPENDENT COMPONENT ANALYSIS PROCESSOR 24
3.1 AN ORICA BASED REAL-TIME MULTI-CHANNEL EEG ACQUISITION SYSTEM ON CHIP DESIGN WITH AUTOMATIC EYE BLINK ARTIFACT REJECTION 25
3.2 DESIGN OF THE MULTI-CHANNEL ORICA PROCESSOR 27
3.2.1 Overall Architecture of the ORICA Processor 28
3.2.2 Preprocessing Unit 31
3.2.3 Singular Value Decomposition Unit 35
3.2.4 Floating Matrix Multiplier Unit 38
3.2.5 ORICA Weight Training Unit 40
CHAPTER 4 EXPERIMENTAL RESULT AND CHIP IMPLEMENTATION 54
4.1 TSMC 90NM 8-CHANNEL ORICA PROCESSOR TAPE-OUT 54
4.1.1 Functional Verification and Power Consumption Analysis 56
4.1.2 Verification Environment 59
4.2 PERFORMANCE ANALYSIS OF THE 8-CHANNEL ORICA PROCESSOR 62
4.2.1 Performance Analysis Using Simulated EEG Patterns 62
4.2.2 Performance Analysis Using Real EEG Patterns 68
4.2.3 Comparison 75
4.3 A PORTABLE REAL-TIME EEG SYSTEM BASED ON THE EEG ACQUISITION SYSTEM ON CHIP DESIGN. 76
CHAPTER 5 CONCLUSION AND FUTURE WORKS 80
5.1 CONCLUSIONS 80
5.2 FUTURE WORKS 82
REFERENCE 83

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