臺灣博碩士論文加值系統

數位電路的優點在於可延伸與可攜帶性，現今以數位方式取代類比功能是非常具有吸引力，近年來發表許多全數位鎖相迴路架構與其商業應用。
本論文提出一個具有Bang-Bang相位偵測器之三迴路全數位頻率合成器，使用低除頻器除率技巧降低全數位鎖相迴路頻寬內之相位雜訊，本電路以台積電180奈米製程實現，數位控制振盪器提供5.2GHz到5.6GHz可調範圍，模擬顯示相位雜訊為-115.8dBc/Hz@1MHz，在供應電壓1.8伏特下總消耗功率為39mW 。

Advantage of the digital circuits is its scalability and portability. Today digital replacement of an analog function is very attractive. In recent years, many all-digital phase-locked loop (ADPLL) architectures and commercial application have been reported.
This thesis presents an all-digital frequency synthesizer with bang-bang phase detectors (BBPD) and a triple loop architecture. A low-divider ratio technique is adopted to suppress the ADPLL in-band phase noise. The proposed circuits were fabricated in TSMC 180nm technology. The digitally-controlled oscillator (DCO) provides the tuning of 5.2-5.6 GHz. The simulated phase noise is equal to -115.8 dBc/Hz at 1MHz offset. The total power dissipation is 39 mW with 1.8V supply voltage.

致謝 i
摘要 ii
Abstract iii
目錄 iv
圖目錄 vi
表目錄 x

第一章 緒論 1
1.1 研究動機 1
1.2 論文概要 1

第二章 鎖相迴路研究 2
2.1 頻率合成器 2
2.2 振盪器分析與壓控振盪器數學模型 3
2.3 數位控制振盪器數學模型 5
2.4 鎖相迴路分析 6
2.4.1 線性模型 6
2.4.2 開迴路分析 7
2.4.3 閉迴路分析 8
2.4.4 雜訊分析 10
2.5 無除頻器頻率合成器 12
2.5.1 低功耗無除頻器頻率合成器 12
2.5.2 低雜訊無除頻器頻率合成器 14
2.5.3 強健式無除頻器頻率合成器 16
2.5.4 小數型次取樣鎖相迴路 19
2.6 全數位鎖相迴路 20

第三章 低除數全數位頻率合成器 23
3.1 電路架構 23
3.2 穩定度分析 25
3.3 全數位鎖相迴路參數設計 28
3.4 系統層級行為模擬 31
第四章 各子電路架構與模擬 36
4.1 相位內插電路 36
4.2 數位正交頻率偵測器 38
4.3 Bang-Bang相位偵測器 41
4.4 高速除頻器與可程式化除頻器 42
4.5 數位控制振盪器 46
4.6 數位濾波器 51
4.7 三角積分調變器 51
4.8 暫態模擬與雜訊計算 55
4.8.1 暫態模擬 55
4.8.2 雜訊計算 56
4.8.3 效能總結 58

第五章 結論 60

參考文獻 61

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