臺灣博碩士論文加值系統

功率放大器（Power Amplifier, PA），除了關係到各種通訊系統的通訊品質外，同時也是系統設備中最消耗功率以及體積較大的電路元件。藉由功率放大器的作用，發射器可將傳輸訊號功率放大，再藉由射頻（Radio Frequency, RF）通道將訊號發送出去。一般而言，功率放大器的應用領域，可涵蓋行動通訊系統、衛星通訊系統、微波通訊系統、以及ISM/WLAN等不同產品。
在射頻積體電路(Radio Frequency Integrated Circuit, RF IC)設計中，射頻功率放大器，一直以來，即是無線通訊系統最關鍵的電路元件之一，其輸出功率(Output Power)與功率增加效率(Power-Added Efficiency, PAE)對於系統的效能與效率有決定性的影響。E類功率放大器的增加效率高且可允許操作在部分非線性模式，使射頻系統的設計更具有彈性。然而目前2.4GHz 互補式金氧半導體(Complementary Metal-Oxide-Semiconductor, CMOS) E類功率放大器，鮮少被完成或是發表出來，即或發表亦常以被動元件採用晶粒外(Off-Chip)設計。
本文提出一個解決單晶片(System-on-Chip, SoC) CMOS元件應用於E類功率放大器的設計，應用單級功率放大器，電晶體用多閘極結構提升整體電路線性度，此外，本電路搭配0.18微米製程中的內建電感與電容做適當的計算與調變阻抗匹配模擬，工作電壓於1.8V，應用於2.4GHz頻段，工業、科學、醫學(Industry-Science-Medicine, ISM)頻道無線通訊系通晶片，並採用台積電(TSMC) 0.18微米CMOS製程參數作運算。此On-Chip功率放大器設計，其模擬結果為輸出功率+21dBm與功率增加效率+35%。

The power amplifier not only dominates the communication quality in many communication systems, but also consumes more power budget in these systems. Because of its power dissipation concern, its device area is also bigger in communication system. Through power amplifier, the transmitter can amplify the transmitted signals. Furthermore, they can pass away through a radio-frequency (RF) channel to deliver the signals far away. Generally, the power amplifier can be employed into many communication fields, such as cellular phones, satellite communication systems, ISM/WLAN products etc.
In this thesis, we propose a possible solution for the system-on-chip (SoC) with CMOS devices in class-E power amplifier issues. Single stage circuits with the built-in inductors and capacitors under 0.18um CMOS process are employed to do the impedance-match simulation. As a result, the circuit simulation results under the suitable calculation and adjustment depict the good performance comparing with the off-chip design. Not only can the power amplifier be integrated into the SoC, but the entire chip cost can be reduced, especially in the chip area and the package cost. Because the full chip cost is reduced more, this power amplifier is very feasible to be applied into wireless communication chips for the 2.4GHz Industry-Science-Medicine (ISM) band.
In this circuit simulation, the process information and the device models with 0.18um CMOS technology are provided by TSMC. The suitable operation voltage of this power amplifier is 2.4V. Furthermore, the simulation software, Advanced Design System (ADS), comes from Agilent company through the Chip Implementation Center (CIC) channel. We obtain the good simulation results of the on-chip power amplifier are the output power, +21 dBm, and the power-added efficiency,+35%.

中文摘要 i
英文摘要 ii
誌謝 iv
目錄 v
表目錄 vii
圖目錄 viii
第一章 緒論 1
1.1研究目的 1
1.2研究方法與步驟 4
第二章 射頻積體電路之觀念 6
2.1導論 6
2.2 TSMC 0.18mm CMOS製程簡介 6
2.2.1 元件模型與電路設計關係 6
2.2.2 NMOS 電晶體 7
2.2.3 MIM電容 8
2.2.4 螺旋型電感 10
2.3非線性效應 13
2.4諧波( Harmonics ) 14
2.5 S參數（S-parameter）介紹與定義 15
2.6功率增益( Power Gain )之定義 17
2.6.1 轉移功率增益( Transducer Power Gain ) – GT 19
2.6.2 操作功率增益( Operation Power Gain ) – GP 20
2.6.3 可用功率增益( Available Power Gain ) – GA 20
2.7增益壓縮( Gain Compression 21
2.8效率( Efficiency ) 22
2.9相互調變( Inter Modulation ) 23
2.10雜訊指數(Noise Figure 26
2.11穩定度(Stability)條件 28
第三章 射頻功率放大器概論 30
3.1 Class A、Class B & Class C射頻功率放大器 30
3.1.1 Class A射頻功率放大器 31
3.1.2 Class B射頻功率放大器 33
3.1.3 Class C射頻功率放大器 35
3.2 Class D、Class E & Class F射頻功率放大器 37
3.2.1 Class D射頻功率放大器 37
3.2.2 Class E射頻功率放大器 39
3.2.3 Class F射頻功率放大器 40
第四章 Class E功率放大器 42
4.1 Class E功率放大器之介紹 42
4.2 Class E功率放大器之操作原理 43
4.3 Class E 功率放大器之設計考量 46
4.4電路分析 47
第五章 Class E功率放大器之設計與模擬 52
5.1導論 52
5.2電路架構 53
5.3匹配網路 54
5.4模擬結果 58
5.4.1 阻抗匹配模擬 58
5.4.2 功率增益模擬 59
5.4.3 反向隔離度模擬 60
5.4.4 1dB壓縮點 61
5.4.5 輸出功率與功率增加效率模擬 62
5.4.6 汲極電壓（Vd=Vout）與汲極電流（Id）模擬 64
5.4.7 穩定度(Stability)模擬 65
5.4.8 IIP3模擬 66
5.4.9 溫度、電壓漂移與製程差異之模擬 67
第六章 結論 70
Reference 72

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